SLAS865F October   2014  – December 2021 MSP430FR4131 , MSP430FR4132 , MSP430FR4133

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Functional Block Diagram
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Signal Descriptions
    3. 7.3 Pin Multiplexing
    4. 7.4 Connection of Unused Pins
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Active Mode Supply Current Per MHz
    6. 8.6  Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
    7. 8.7  Low-Power Mode LPM3, LPM4 Supply Currents (Into VCC) Excluding External Current
    8. 8.8  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    9. 8.9  Typical Characteristics, Low-Power Mode Supply Currents
    10. 8.10 Current Consumption Per Module
    11. 8.11 Thermal Characteristics
    12. 8.12 Timing and Switching Characteristics
      1. 8.12.1  Power Supply Sequencing
        1. 8.12.1.1 PMM, SVS and BOR
      2. 8.12.2  Reset Timing
        1. 8.12.2.1 Wake-up Times From Low-Power Modes and Reset
      3. 8.12.3  Clock Specifications
        1. 8.12.3.1 XT1 Crystal Oscillator (Low Frequency)
        2. 8.12.3.2 DCO FLL, Frequency
        3. 8.12.3.3 REFO
        4. 8.12.3.4 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        5. 8.12.3.5 Module Oscillator Clock (MODCLK)
      4. 8.12.4  Digital I/Os
        1. 8.12.4.1 Digital Inputs
        2. 8.12.4.2 Digital Outputs
        3. 8.12.4.3 Digital I/O Typical Characteristics
      5. 8.12.5  Timer_A
        1. 8.12.5.1 Timer_A
      6. 8.12.6  eUSCI
        1. 8.12.6.1 eUSCI (UART Mode) Operating Frequency
        2. 8.12.6.2 eUSCI (UART Mode) Switching Characteristics
        3. 8.12.6.3 eUSCI (SPI Master Mode) Operating Frequency
        4. 8.12.6.4 eUSCI (SPI Master Mode) Switching Characteristics
        5. 8.12.6.5 eUSCI (SPI Slave Mode) Switching Characteristics
        6. 8.12.6.6 eUSCI (I2C Mode) Switching Characteristics
      7. 8.12.7  ADC
        1. 8.12.7.1 ADC, Power Supply and Input Range Conditions
        2. 8.12.7.2 ADC, 10-Bit Timing Parameters
        3. 8.12.7.3 ADC, 10-Bit Linearity Parameters
      8. 8.12.8  LCD Controller
        1. 8.12.8.1 LCD Recommended Operating Conditions
      9. 8.12.9  FRAM
        1. 8.12.9.1 FRAM
      10. 8.12.10 Emulation and Debug
        1. 8.12.10.1 JTAG and Spy-Bi-Wire Interface
  9. 9 Detailed Description
    1. 9.1  CPU
    2. 9.2  Operating Modes
    3. 9.3  Interrupt Vector Addresses
    4. 9.4  Bootloader (BSL)
    5. 9.5  JTAG Standard Interface
    6. 9.6  Spy-Bi-Wire Interface (SBW)
    7. 9.7  FRAM
    8. 9.8  Memory Protection
    9. 9.9  Peripherals
      1. 9.9.1  Power Management Module (PMM) and On-Chip Reference Voltages
      2. 9.9.2  Clock System (CS) and Clock Distribution
      3. 9.9.3  General-Purpose Input/Output Port (I/O)
      4. 9.9.4  Watchdog Timer (WDT)
      5. 9.9.5  System Module (SYS)
      6. 9.9.6  Cyclic Redundancy Check (CRC)
      7. 9.9.7  Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
      8. 9.9.8  Timers (Timer0_A3, Timer1_A3)
      9. 9.9.9  Real-Time Clock (RTC) Counter
      10. 9.9.10 10-Bit Analog Digital Converter (ADC)
      11. 9.9.11 Liquid Crystal Display (LCD)
      12. 9.9.12 Embedded Emulation Module (EEM)
      13. 9.9.13 Input/Output Schematics
        1. 9.9.13.1  Port P1 Input/Output With Schmitt Trigger
        2. 9.9.13.2  Port P2 Input/Output With Schmitt Trigger
        3. 9.9.13.3  Port P3 Input/Output With Schmitt Trigger
        4. 9.9.13.4  Port P4.0 Input/Output With Schmitt Trigger
        5. 9.9.13.5  Port P4.1 and P4.2 Input/Output With Schmitt Trigger
        6. 9.9.13.6  Port 4.3, P4.4, P4.5, P4.6, and P4.7 Input/Output With Schmitt Trigger
        7. 9.9.13.7  Port P5.0, P5.1, P5.2, and P5.3 Input/Output With Schmitt Trigger
        8. 9.9.13.8  Port P5.4, P5.5, P5.6, and P5.7 Input/Output With Schmitt Trigger
        9. 9.9.13.9  Port P6 Input/Output With Schmitt Trigger
        10. 9.9.13.10 Port P7 Input/Output With Schmitt Trigger
        11. 9.9.13.11 Port P8.0 and P8.1 Input/Output With Schmitt Trigger
        12. 9.9.13.12 Port P8.2 and P8.3 Input/Output With Schmitt Trigger
    10. 9.10 Device Descriptors (TLV)
    11. 9.11 Memory
      1. 9.11.1 Peripheral File Map
    12. 9.12 Identification
      1. 9.12.1 Revision Identification
      2. 9.12.2 Device Identification
      3. 9.12.3 JTAG Identification
  10. 10Applications, Implementation, and Layout
    1. 10.1 Device Connection and Layout Fundamentals
      1. 10.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 10.1.2 External Oscillator
      3. 10.1.3 JTAG
      4. 10.1.4 Reset
      5. 10.1.5 Unused Pins
      6. 10.1.6 General Layout Recommendations
      7. 10.1.7 Do's and Don'ts
    2. 10.2 Peripheral- and Interface-Specific Design Information
      1. 10.2.1 ADC Peripheral
        1. 10.2.1.1 Partial Schematic
        2. 10.2.1.2 Design Requirements
        3. 10.2.1.3 Layout Guidelines
      2. 10.2.2 LCD_E Peripheral
        1. 10.2.2.1 Partial Schematic
        2. 10.2.2.2 Design Requirements
        3. 10.2.2.3 Detailed Design Procedure
        4. 10.2.2.4 Layout Guidelines
      3. 10.2.3 Timer
        1. 10.2.3.1 Generate Accurate PWM Using Internal Oscillator
    3. 10.3 Typical Applications
  11. 11Device and Documentation Support
    1. 11.1 Getting Started
    2. 11.2 Device Nomenclature
    3. 11.3 Tools and Software
    4. 11.4 Documentation Support
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Export Control Notice
    9. 11.9 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.2 Signal Descriptions

Section 7.2 describes the signals for all device variants and package options.

Table 7-1 Signal Descriptions
TERMINAL I/O DESCRIPTION
NAME PACKAGE SUFFIX
PM G56 G48
P4.7/R13 1 7 7 I/O General-purpose I/O
Input/output port of third most positive analog LCD voltage V4
P4.6/R23 2 8 8 I/O General-purpose I/O
Input/output port of second most positive analog LCD voltage V2
P4.5/R33 3 9 9 I/O General-purpose I/O
Input/output port of first most positive analog LCD voltage V1
P4.4/LCDCAP1 4 10 10 I/O General-purpose I/O
LCD charge pump external port connecting to LCDCAP0 pin by 0.1‑µF capacitor
P4.3/LCDCAP0 5 11 11 I/O General-purpose I/O
LCD charge pump external port connecting to LCDCAP1 pin by 0.1‑µF capacitor
P4.2/XOUT 6 12 12 I/O General-purpose I/O
Output terminal for crystal oscillator
P4.1/XIN 7 13 13 I/O General-purpose I/O
Input terminal for crystal oscillator
DVSS 8 14 14 Power ground
DVCC 9 15 15 Power supply
RST/NMI/SBWTDIO 10 16 16 I/O Reset input active low
Nonmaskable interrupt input
Spy-Bi-Wire data input/output
TEST/SBWTCK 11 17 17 I Test Mode pin – selected digital I/O on JTAG pins
Spy-Bi-Wire input clock
P4.0/TA1.1 12 18 18 I/O General-purpose I/O
Timer TA1 CCR1 capture: CCI1A input, compare: Out1 outputs
P8.3/TA1.2(1) 13 19 – I/O General-purpose I/O
Timer TA1 CCR2 capture: CCI2A input, compare: Out2 outputs
P8.2/TA1CLK(1) 14 20 – I/O General-purpose I/O
Timer clock input TACLK for TA1
P8.1/ACLK/A9(1) 15 – – I/O General-purpose I/O
ACLK output
Analog input A9
P8.0/SMCLK/A8(1) 16 – – I/O General-purpose I/O
SMCLK output
Analog input A8
P1.7/TA0.1/TDO/A7 17 21 19 I/O General-purpose I/O(2)
Timer TA0 CCR1 capture: CCI1A input, compare: Out1 outputs
Test data output
Analog input A7
P1.6/TA0.2/TDI/TCLK/A6 18 22 20 I/O General-purpose I/O(2)
Timer TA0 CCR2 capture: CCI2A input, compare: Out2 outputs
Test data input or test clock input
Analog input A6
P1.5/TA0CLK/TMS/A5 19 23 21 I/O General-purpose I/O(2)
Timer clock input TACLK for TA0
Test mode select
Analog input A5
P1.4/MCLK/TCK/A4/VREF+ 20 24 22 I/O General-purpose I/O(2)
MCLK output
Test clock
Analog input A4
Output of positive reference voltage with ground as reference
P1.3/UCA0STE/A3 21 25 23 I/O General-purpose I/O
eUSCI_A0 SPI slave transmit enable
Analog input A3
P1.2/UCA0CLK/A2 22 26 24 I/O General-purpose I/O
eUSCI_A0 SPI clock input/output
Analog input A2
P1.1/UCA0RXD/UCA0SOMI/ A1/Veref+ 23 27 25 I/O General-purpose I/O
eUSCI_A0 UART receive data
eUSCI_A0 SPI slave out/master in
Analog input A1, and ADC positive reference
P1.0/UCA0TXD/UCA0SIMO/ A0/Veref- 24 28 26 I/O General-purpose I/O
eUSCI_A0 UART transmit data
eUSCI_A0 SPI slave in/master out
Analog input A0, and ADC negative reference
P5.7/L39(1) 25 – – I/O General-purpose I/O
LCD drive pin; either segment or common output
P5.6/L38(1) 26 – – I/O General-purpose I/O
LCD drive pin; either segment or common output
P5.5/L37(1) 27 29 – I/O General-purpose I/O
LCD drive pin; either segment or common output
P5.4/L36(1) 28 30 – I/O General-purpose I/O
LCD drive pin; either segment or common output
P5.3/UCB0SOMI/UCB0SCL/L35 29 31 27 I/O General-purpose I/O
eUSCI_B0 SPI slave out/master in; eUSCI_B0 I2C clock
LCD drive pin; either segment or common output
P5.2/UCB0SIMO/UCB0SDA/L34 30 32 28 I/O General-purpose I/O
eUSCI_B0 SPI slave in/master out; eUSCI_B0 I2C data
LCD drive pin; either segment or common output
P5.1/UCB0CLK/L33 31 33 29 I/O General-purpose I/O
eUSCI_B0 clock input/output
LCD drive pin; either segment or common output
P5.0/UCB0STE/L32 32 34 30 I/O General-purpose I/O
eUSCI_B0 slave transmit enable
LCD drive pin; either segment or common output
P2.7/L31 33 35 31 I/O General-purpose I/O
LCD drive pin; either segment or common output
P2.6/L30 34 36 32 I/O General-purpose I/O
LCD drive pin; either segment or common output
P2.5/L29 35 37 33 I/O General-purpose I/O
LCD drive pin; either segment or common output
P2.4/L28 36 38 34 I/O General-purpose I/O
LCD drive pin; either segment or common output
P2.3/L27 37 39 35 I/O General-purpose I/O
LCD drive pin; either segment or common output
P2.2/L26 38 40 36 I/O General-purpose I/O
LCD drive pin; either segment or common output
P2.1/L25 39 41 37 I/O General-purpose I/O
LCD drive pin; either segment or common output
P2.0/L24 40 42 38 I/O General-purpose I/O
LCD drive pin; either segment or common output
P6.7/L23(1) 41 – – I/O General-purpose I/O
LCD drive pin; either segment or common output
P6.6/L22(1) 42 – – I/O General-purpose I/O
LCD drive pin; either segment or common output
P6.5/L21(1) 43 43 – I/O General-purpose I/O
LCD drive pin; either segment or common output
P6.4/L20(1) 44 44 – I/O General-purpose I/O
LCD drive pin; either segment or common output
P6.3/L19 45 45 39 I/O General-purpose I/O
LCD drive pin; either segment or common output
P6.2/L18 46 46 40 I/O General-purpose I/O
LCD drive pin; either segment or common output
P6.1/L17 47 47 41 I/O General-purpose I/O
LCD drive pin; either segment or common output
P6.0/L16 48 48 42 I/O General-purpose I/O
LCD drive pin; either segment or common output
P3.7/L15 49 49 43 I/O General-purpose I/O
LCD drive pin; either segment or common output
P3.6/L14 50 50 44 I/O General-purpose I/O
LCD drive pin; either segment or common output
P3.5/L13 51 51 45 I/O General-purpose I/O
LCD drive pin; either segment or common output
P3.4/L12 52 52 46 I/O General-purpose I/O
LCD drive pin; either segment or common output
P3.3/L11 53 53 47 I/O General-purpose I/O
LCD drive pin; either segment or common output
P3.2/L10 54 54 48 I/O General-purpose I/O
LCD drive pin; either segment or common output
P3.1/L9 55 55 1 I/O General-purpose I/O
LCD drive pin; either segment or common output
P3.0/L8 56 56 2 I/O General-purpose I/O
LCD drive pin; either segment or common output
P7.7/L7(1) 57 – – I/O General-purpose I/O
LCD drive pin; either segment or common output
P7.6/L6(1) 58 – – I/O General-purpose I/O
LCD drive pin; either segment or common output
P7.5/L5(1) 59 1 – I/O General-purpose I/O
LCD drive pin; either segment or common output
P7.4/L4(1) 60 2 – I/O General-purpose I/O
LCD drive pin; either segment or common output
P7.3/L3 61 3 3 I/O General-purpose I/O
LCD drive pin; either segment or common output
P7.2/L2 62 4 4 I/O General-purpose I/O
LCD drive pin; either segment or common output
P7.1/L1 63 5 5 I/O General-purpose I/O
LCD drive pin; either segment or common output
P7.0/L0 64 6 6 I/O General-purpose I/O
LCD drive pin; either segment or common output
(1) Any pin that is not bonded out in a smaller package must be initialized by software after reset to achieve the lowest leakage current.
(2) Because this pin is multiplexed with the JTAG function, TI recommends disabling the pin interrupt function while in JTAG debug to prevent collisions.