TI recommends powering AVCC and DVCC pins from the same source. At a minimum, during power up, power down, and device operation, the voltage difference between AVCC and DVCC must not exceed the limits specified in Absolute Maximum Ratings. Exceeding the specified limits may cause malfunction of the device including erroneous writes to RAM and FRAM.
At power up, the device does not start executing code before the supply voltage reaches VSVSH+ if the supply rises monotonically to this level.
Table 5-1 lists the reset power ramp requirements.