SLASEF5B Data sheet

SLASEF5B January 2019 – December 2021 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

PN|80
- MTQF010B

Thermal pad, mechanical data (Package|Pins)

Orderable Information

7.2 Pin Attributes

Table 7-1 Pin Attributes

PIN NUMBER⁽¹⁾		SIGNAL NAME⁽¹⁾⁽⁴⁾	SIGNAL TYPE⁽²⁾	BUFFER TYPE⁽³⁾	POWER SOURCE⁽⁵⁾	RESET STATE AFTER BOR⁽⁷⁾
FR6043, FR6041	FR5043, FR5041	SIGNAL NAME⁽¹⁾⁽⁴⁾	SIGNAL TYPE⁽²⁾	BUFFER TYPE⁽³⁾	POWER SOURCE⁽⁵⁾	RESET STATE AFTER BOR⁽⁷⁾
1	1	AVCC1	P	Power	–	N/A
2	2	P2.2	I/O	LVCMOS	DVCC	OFF
		COUT	O	LVCMOS	DVCC	–
		UCA0CLK	I/O	LVCMOS	DVCC	–
		A14	I	Analog	DVCC	–
		C14	I	Analog	DVCC	–
3	–	P2.3	I/O	LVCMOS	DVCC	OFF
		TA0.0	I/O	LVCMOS	DVCC	–
		UCA0STE	I/O	LVCMOS	DVCC	–
		A15	I	Analog	DVCC	–
		C15	I	Analog	DVCC	–
4	3	P1.0	I/O	LVCMOS	DVCC	OFF
		UCA1CLK	I/O	LVCMOS	DVCC	–
		TA1.0	I/O	LVCMOS	DVCC	–
		A0	I	Analog	DVCC	–
		C0	I	Analog	DVCC	–
		VREF-	O	Analog	DVCC	–
		VeREF-	I	Analog	DVCC	–
5	4	P1.1	I/O	LVCMOS	DVCC	OFF
		UCA1STE	I/O	LVCMOS	DVCC	–
		TA4.0	I/O	LVCMOS	DVCC	–
		A1	I	Analog	DVCC	–
		C1	I	Analog	DVCC	–
		VREF+	O	Analog	DVCC	–
		VeREF+	I	Analog	DVCC	–
6	5	AVSS2	P	Power	–	N/A
7	6	PJ.4	I/O	LVCMOS	DVCC	OFF
7	6	LFXIN	I	Analog	DVCC	–
8	7	PJ.5	I/O	LVCMOS	DVCC	OFF
8	7	LFXOUT	O	Analog	DVCC	–
9	8	AVSS3	P	Power	–	N/A
10	9	PJ.6	I/O	LVCMOS	DVCC	–
		HFXIN	I	Analog	DVCC	–
		USSXT_BOUT	O	Analog	DVCC	–
11	10	PJ.7	I/O	LVCMOS	DVCC	OFF
11	10	HFXOUT	O	Analog	DVCC	–
12	–	P2.4	I/O	LVCMOS	DVCC	OFF
		TA0CLK	I	LVCMOS	DVCC	–
		TB0CLK	I	LVCMOS	DVCC	–
		TA1CLK	I	LVCMOS	DVCC	–
		S24	O	Analog	DVCC	–
13	–	P2.6	I/O	LVCMOS	DVCC	OFF
		UCA0TXD	O	LVCMOS	DVCC	–
		UCA0SIMO	I/O	LVCMOS	DVCC	–
		TA1.2	I/O	LVCMOS	DVCC	–
		TA1.2C	I/O	LVCMOS	DVCC	–
		S23	O	Analog	DVCC	–
14	–	P2.7	I/O	LVCMOS	DVCC	OFF
		UCA0RXD	I	LVCMOS	DVCC	–
		UCA0SOMI	I/O	LVCMOS	DVCC	–
		TA4.1	I/O	LVCMOS	DVCC	–
		TA4.1C	I/O	LVCMOS	DVCC	–
		S22	O	Analog	DVCC	–
15	11	TEST	I	LVCMOS	DVCC	PD
15	11	SBWTCK	I	LVCMOS	DVCC	–
16	12	RST	I/O	LVCMOS	DVCC	PU
		NMI	I	LVCMOS	DVCC	–
		SBWTDIO	I/O	LVCMOS	DVCC	–
17	13	PJ.0	I/O	LVCMOS	DVCC	OFF
		TDO	O	LVCMOS	DVCC	–
		UCA2CLK	I/O	LVCMOS	DVCC	–
		SRSCG1	O	LVCMOS	DVCC	–
		DMAE0	I	LVCMOS	DVCC	–
		C10	I	Analog	DVCC	–
18	14	PJ.1	I/O	LVCMOS	DVCC	OFF
		TDI	I	LVCMOS	DVCC	–
		TCLK	I	LVCMOS	DVCC	–
		UCA2STE	I/O	LVCMOS	DVCC	–
		SRSCG0	O	LVCMOS	DVCC	–
		TA4CLK	I	LVCMOS	DVCC	–
		C11	I	Analog	DVCC	–
19	15	PJ.2	I/O	LVCMOS	DVCC	OFF
		TMS	I	LVCMOS	DVCC	–
		UCA2TXD	O	LVCMOS	DVCC	–
		UCA2SIMO	I/O	LVCMOS	DVCC	–
		SROSCOFF	O	LVCMOS	DVCC	–
		TB0OUTH	I	LVCMOS	DVCC	–
		C12	I	Analog	DVCC	–
20	16	PJ.3	I/O	LVCMOS	DVCC	OFF
		TCK	I	LVCMOS	DVCC	–
		UCA2RXD	I	LVCMOS	DVCC	–
		UCA2SOMI	I/O	LVCMOS	DVCC	–
		SRCPUOFF	O	LVCMOS	DVCC	–
		TB0.6	I/O	LVCMOS	DVCC	–
		C13	I	Analog	DVCC	–
21	17	DVSS1	P	Power	–	N/A
22	18	DVCC1	P	Power	–	N/A
23	–	P2.5	I/O	LVCMOS	DVCC	OFF
		TA0.2	I/O	LVCMOS	DVCC	–
		TA4.0	I/O	LVCMOS	DVCC	–
		S21	O	Analog	DVCC	–
24	–	P3.0	I/O	LVCMOS	DVCC	OFF
		TB0.0	I/O	LVCMOS	DVCC	–
		S20	O	Analog	DVCC	–
25	19	P1.2	I/O	LVCMOS	DVCC	OFF
		UCA1TXD	O	LVCMOS	DVCC	–
		UCA1SIMO	I/O	LVCMOS	DVCC	–
		TA1.0	I/O	LVCMOS	DVCC	–
		A8	I	Analog	DVCC	–
		C8	I	Analog	DVCC	–
26	20	P1.3	I/O	LVCMOS	DVCC	OFF
		UCA1RXD	I	LVCMOS	DVCC	–
		UCA1SOMI	I/O	LVCMOS	DVCC	–
		TA1.1	I/O	LVCMOS	DVCC	–
		A9	I	Analog	DVCC	–
		C9	I	Analog	DVCC	–
27	21	P2.0	I/O	LVCMOS	DVCC	OFF
		UCA1CLK	I/O	LVCMOS	DVCC	–
		UCA3TXD	O	LVCMOS	DVCC	–
		UCA3SIMO	I/O	LVCMOS	DVCC	–
		S19	O	Analog	DVCC	–
28	22	P2.1	I/O	LVCMOS	DVCC	OFF
		UCA1STE	I/O	LVCMOS	DVCC	–
		UCA3RXD	I	LVCMOS	DVCC	–
		UCA3SOMI	I/O	LVCMOS	DVCC	–
		S18	O	Analog	DVCC	–
29	23	P1.6	I/O	LVCMOS	DVCC	OFF
		UCA3STE	I/O	LVCMOS	DVCC	–
		UCB0SIMO	I/O	LVCMOS	DVCC	–
		UCB0SDA	I/O	LVCMOS	DVCC	–
		S17	O	Analog	DVCC	–
30	24	P1.7	I/O	LVCMOS	DVCC	OFF
		USSTRG	I	LVCMOS	DVCC	–
		UCA3CLK	I/O	LVCMOS	DVCC	–
		UCB0SOMI	I/O	LVCMOS	DVCC	–
		UCB0SCL	I/O	LVCMOS	DVCC	–
		S16	O	Analog	DVCC	–
31	25	P1.4	I/O	LVCMOS	DVCC	OFF
		TB0.4	I/O	LVCMOS	DVCC	–
		UCA0STE	I/O	LVCMOS	DVCC	–
		A2	I	Analog	DVCC	–
		C2	I	Analog	DVCC	–
32	26	P1.5	I/O	LVCMOS	DVCC	OFF
		TB0.5	I/O	LVCMOS	DVCC	–
		UCB0CLK	I/O	LVCMOS	DVCC	–
		A3	I	Analog	DVCC	–
		C3	I	Analog	DVCC	–
33	27	P3.1	I/O	LVCMOS	DVCC	OFF
		TA1CLK	I	LVCMOS	DVCC	–
		TB0.1	I/O	LVCMOS	DVCC	–
		MTIF_OUT_IN	I/O	LVCMOS	DVCC	–
34	28	P4.0	I/O	LVCMOS	DVCC	OFF
		RTCCLK	O	LVCMOS	DVCC	–
		TA4.1	O	LVCMOS	DVCC	–
		MTIF_PIN_EN	I	LVCMOS	DVCC	–
35	29	P4.1	I/O	LVCMOS	DVCC	OFF
		UCA0CLK	I/O	LVCMOS	DVCC	–
		TB0.4	I/O	LVCMOS	DVCC	–
		UCA3RXD	I	LVCMOS	DVCC	–
		UCA3SOMI	I/O	LVCMOS	DVCC	–
		S15	O	Analog	DVCC	–
36	30	P4.2	I/O	LVCMOS	DVCC	OFF
		UCA0STE	I/O	LVCMOS	DVCC	–
		TB0.5	I/O	LVCMOS	DVCC	–
		UCA3SIMO	I/O	LVCMOS	DVCC	–
		UCA3TXD	O	LVCMOS	DVCC	–
		S14	O	Analog	DVCC	–
37	31	P4.3	I/O	LVCMOS	DVCC	OFF
		UCA0TXD	O	LVCMOS	DVCC	–
		UCA0SIMO	I/O	LVCMOS	DVCC	–
		S13	O	Analog	DVCC	–
38	32	P4.4	I/O	LVCMOS	DVCC	OFF
		UCA0RXD	I	LVCMOS	DVCC	–
		UCA0SOMI	I/O	LVCMOS	DVCC	–
		S12	O	Analog	DVCC	–
39	–	P4.5	I/O	LVCMOS	DVCC	OFF
		TA0CLK	I	LVCMOS	DVCC	–
		TA1CLK	I	LVCMOS	DVCC	–
		S11	O	Analog	DVCC	–
40	–	P4.6	I/O	LVCMOS	DVCC	OFF
		TB0CLK	I	LVCMOS	DVCC	–
		TA4CLK	I	LVCMOS	DVCC	–
		S10	O	Analog	DVCC	–
41	33	DVSS2	P	Power	–	N/A
42	–	P4.7	I/O	LVCMOS	DVCC	OFF
		DMAE0	I	LVCMOS	DVCC	–
		S9	O	Analog	DVCC	–
43	34	P5.0	I/O	LVCMOS	DVCC	OFF
		TB0.0	I/O	LVCMOS	DVCC	–
		UCA2TXD	O	LVCMOS	DVCC	–
		UCA2SIMO	I/O	LVCMOS	DVCC	–
		S8	O	Analog	DVCC	–
44	35	P5.1	I/O	LVCMOS	DVCC	OFF
		TB0.1	O	LVCMOS	DVCC	–
		UCA2RXD	I	LVCMOS	DVCC	–
		UCA2SOMI	I/O	LVCMOS	DVCC	–
		S7	O	Analog	DVCC	–
45	36	P5.2	I/O	LVCMOS	DVCC	OFF
		TB0.2	O	LVCMOS	DVCC	–
		UCA2CLK	I/O	LVCMOS	DVCC	–
		S6	O	Analog	DVCC	–
46	37	P5.3	I/O	LVCMOS	DVCC	OFF
		TB0.3	O	LVCMOS	DVCC	–
		UCA2STE	I/O	LVCMOS	DVCC	–
		S5	O	Analog	DVCC	–
47	38	P5.4	I/O	LVCMOS	DVCC	OFF
		TA0.0	I/O	LVCMOS	DVCC	–
		UCB1CLK	I/O	LVCMOS	DVCC	–
		TA4.0	O	LVCMOS	DVCC	–
		S4	O	Analog	DVCC	–
48	39	P5.5	I/O	LVCMOS	DVCC	OFF
		TA4.1	I/O	LVCMOS	DVCC	–
		UCB1SIMO	I/O	LVCMOS	DVCC	–
		UCB1SDA	I/O	LVCMOS	DVCC	–
		S3	O	Analog	DVCC	–
49	40	P5.6	I/O	LVCMOS	DVCC	OFF
		TB0OUTH	I	LVCMOS	DVCC	–
		UCB1SOMI	I/O	LVCMOS	DVCC	–
		UCB1SCL	I/O	LVCMOS	DVCC	–
		S2	O	Analog	DVCC	–
50	41	P5.7	I/O	LVCMOS	DVCC	OFF
		TA0.2	I/O	LVCMOS	DVCC	–
		UCB1STE	I/O	LVCMOS	DVCC	–
		S1	O	Analog	DVCC	–
51	42	P6.0	I/O	LVCMOS	DVCC	OFF
		TA0CLK	I	LVCMOS	DVCC	–
		COUT	I	LVCMOS	DVCC	–
		S0	O	Analog	DVCC	–
52	43	P6.4	I/O	LVCMOS	DVCC	OFF
		MCLK	O	LVCMOS	DVCC	–
		COM0	O	Analog	DVCC	–
53	44	P6.5	I/O	LVCMOS	DVCC	OFF
		SMCLK	O	LVCMOS	DVCC	–
		COM1	O	Analog	DVCC	–
		S34	O	Analog	DVCC	–
54	45	P6.6	I/O	LVCMOS	DVCC	OFF
		ACLK	O	LVCMOS	DVCC	–
		COM2	O	Analog	DVCC	–
		S31	O	Analog	DVCC	–
55	46	P7.0	I/O	LVCMOS	DVCC	OFF
		TA1.0	I/O	LVCMOS	DVCC	–
		TA1.2	I/O	LVCMOS	DVCC	–
		XPB0	O	Analog	1.5 V	–
		S30	O	Analog	DVCC	–
56	–	P6.1	I/O	LVCMOS	DVCC	OFF
		RTCCLK	O	LVCMOS	DVCC	–
		R03	I/O	Analog	DVCC	–
		S33	O	Analog	DVCC	–
57	47	P6.2	I/O	LVCMOS	DVCC	OFF
		TB0CLK	I	LVCMOS	DVCC	–
		R13	I/O	Analog	DVCC	–
		LCDREF	I	Analog	-	–
		S32	O	Analog	DVCC	–
58	48	DVSS3	P	Power	–	N/A
59	49	DVCC3	P	Power	–	N/A
60	–	P6.3	I/O	LVCMOS	DVCC	OFF
		COM7	O	Analog	DVCC	–
		R23	I/O	Analog	DVCC	–
61	–	R33	I/O	Analog	DVCC	-
61	–	LCDCAP	I/O	Analog	DVCC	–
62	–	P6.7	I/O	LVCMOS	DVCC	OFF
		TA0.1	I/O	LVCMOS	DVCC	–
		COM4	O	Analog	DVCC	–
		S29	O	Analog	DVCC	–
63	–	P3.2	I/O	LVCMOS	DVCC	OFF
		TA1.1	I/O	LVCMOS	DVCC	–
		COM5	O	Analog	DVCC	–
		S28	O	Analog	DVCC	–
64	50	P3.3	I/O	LVCMOS	DVCC	OFF
		MCLK	O	LVCMOS	DVCC	–
		TB0.3	I/O	LVCMOS	DVCC	–
		XPB1	O	Analog	1.5 V	–
		S25	O	Analog	DVCC	–
65	51	P3.4	I/O	LVCMOS	DVCC	OFF
		SMCLK	O	LVCMOS	DVCC	–
		COM6	O	Analog	DVCC	–
		DMAE0	I	LVCMOS	DVCC	–
		S27	O	Analog	DVCC	–
66	52	P3.5	I/O	LVCMOS	DVCC	OFF
		ACLK	O	LVCMOS	DVCC	–
		COM3	O	Analog	DVCC	–
		COUT	O	LVCMOS	DVCC	–
		S26	O	Analog	DVCC	–
67	53	CH1_IN	I	Analog	PVCC	–
68	54	CH1_OUT	O	Analog	PVCC	–
69	55	PVSS	P	Power	–	N/A
70	56	PVCC	P	Power	–	N/A
71	57	PVCC	P	Power	–	N/A
72	58	PVSS	P	Power	–	N/A
73	59	CH0_OUT	O	Analog	PVCC	–
74	60	CH0_IN	I	Analog	PVCC	–
75	–	P3.6	I/O	LVCMOS	DVCC	OFF
		UCB1SIMO	I/O	LVCMOS	DVCC	–
		UCB1SDA	I/O	LVCMOS	DVCC	–
		TB0.6	I/O	LVCMOS	DVCC	–
		USSXT_BOUT	I/O	LVCMOS	DVCC	–
		S35	O	Analog	DVCC	–
76	–	P3.7	I/O	LVCMOS	DVCC	OFF
		UCB1SOMI	I/O	LVCMOS	DVCC	–
		UCB1SCL	I/O	LVCMOS	DVCC	–
		TB0.2	I/O	LVCMOS	DVCC	–
		TB0OUTH	I	LVCMOS	DVCC	–
		S36	O	Analog	DVCC	–
77	61	AVSS4	P	Power	–	N/A
78	62	USSXTIN⁽⁶⁾	I	Analog	1.5 V	–
79	63	USSXTOUT⁽⁶⁾	O	Analog	1.5 V	–
80	64	AVSS1	P	Power	–	N/A

(1) The signal that is listed first for each pin is the reset default pin name.

(2) Signal Types: I = Input, O = Output, I/O = Input or Output.

(3) Buffer Types: LVCMOS, Analog, or Power (see Table 7-3 for details)

(4) To determine the pin mux encodings for each pin, see Section 9.14.

(5) The power source shown in this table is the I/O power source, which may differ from the module power source.

(6) Do not connect the USSXTIN and USSXTOUT pins to AVCC or DVCC. USSXTIN does not support bypass mode, so do not drive an external clock to USSXTIN pin.

(7) Reset States:
OFF = High impedance with Schmitt-trigger input and pullup or pulldown (if available) disabled
PU = Pullup is enabled
PD = Pulldown is enabled
N/A = Not applicable