SLASE23E January   2015  – August 2018 MSP430FR6820 , MSP430FR6822 , MSP430FR68221 , MSP430FR6870 , MSP430FR6872 , MSP430FR68721 , MSP430FR6920 , MSP430FR6922 , MSP430FR69221 , MSP430FR6970 , MSP430FR6972 , MSP430FR69721

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. Table 4-2 Signal Descriptions
    4. 4.4 Pin Multiplexing
    5. 4.5 Buffer Type
    6. 4.6 Connection of Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Typical Characteristics - Active Mode Supply Currents
    6. 5.6  Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
    7. 5.7  Low-Power Mode LPM2, LPM3, LPM4 Supply Currents (Into VCC) Excluding External Current
    8. 5.8  Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    9. 5.9  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    10. 5.10 Typical Characteristics, Low-Power Mode Supply Currents
    11. 5.11 Typical Characteristics, Current Consumption per Module
    12. 5.12 Thermal Resistance Characteristics
    13. 5.13 Timing and Switching Characteristics
      1. 5.13.1  Power Supply Sequencing
        1. Table 5-1 Brownout and Device Reset Power Ramp Requirements
        2. Table 5-2 SVS
      2. 5.13.2  Reset Timing
        1. Table 5-3 Reset Input
      3. 5.13.3  Clock Specifications
        1. Table 5-4 Low-Frequency Crystal Oscillator, LFXT
        2. Table 5-5 High-Frequency Crystal Oscillator, HFXT
        3. Table 5-6 DCO
        4. Table 5-7 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        5. Table 5-8 Module Oscillator (MODOSC)
      4. 5.13.4  Wake-up Characteristics
        1. Table 5-9   Wake-up Times From Low-Power Modes and Reset
        2. Table 5-10 Typical Wake-up Charge
        3. 5.13.4.1    Typical Characteristics, Average LPM Currents vs Wake-up Frequency
      5. 5.13.5  Digital I/Os
        1. Table 5-11 Digital Inputs
        2. Table 5-12 Digital Outputs
        3. 5.13.5.1    Typical Characteristics, Digital Outputs at 3.0 V and 2.2 V
        4. Table 5-13 Pin-Oscillator Frequency, Ports Px
        5. 5.13.5.2    Typical Characteristics, Pin-Oscillator Frequency
      6. 5.13.6  Timer_A and Timer_B
        1. Table 5-14 Timer_A
        2. Table 5-15 Timer_B
      7. 5.13.7  eUSCI
        1. Table 5-16 eUSCI (UART Mode) Clock Frequency
        2. Table 5-17 eUSCI (UART Mode)
        3. Table 5-18 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 5-19 eUSCI (SPI Master Mode)
        5. Table 5-20 eUSCI (SPI Slave Mode)
        6. Table 5-21 eUSCI (I2C Mode)
      8. 5.13.8  Segment LCD Controller
        1. Table 5-22 LCD_C Recommended Operating Conditions
        2. Table 5-23 LCD_C Electrical Characteristics
      9. 5.13.9  ADC12
        1. Table 5-24 12-Bit ADC, Power Supply and Input Range Conditions
        2. Table 5-25 12-Bit ADC, Timing Parameters
        3. Table 5-26 12-Bit ADC, Linearity Parameters With External Reference
        4. Table 5-27 12-Bit ADC, Dynamic Performance for Differential Inputs With External Reference
        5. Table 5-28 12-Bit ADC, Dynamic Performance for Differential Inputs With Internal Reference
        6. Table 5-29 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With External Reference
        7. Table 5-30 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With Internal Reference
        8. Table 5-31 12-Bit ADC, Dynamic Performance With 32.768-kHz Clock
        9. Table 5-32 12-Bit ADC, Temperature Sensor and Built-In V1/2
        10. Table 5-33 12-Bit ADC, External Reference
      10. 5.13.10 REF Module
        1. Table 5-34 REF, Built-In Reference
      11. 5.13.11 Comparator
        1. Table 5-35 Comparator_E
      12. 5.13.12 FRAM Controller
        1. Table 5-36 FRAM
      13. 5.13.13 Emulation and Debug
        1. Table 5-37 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Operating Modes
      1. 6.3.1 Peripherals in Low-Power Modes
      2. 6.3.2 Idle Currents of Peripherals in LPM3 and LPM4
    4. 6.4  Interrupt Vector Table and Signatures
    5. 6.5  Bootloader (BSL)
    6. 6.6  JTAG Operation
      1. 6.6.1 JTAG Standard Interface
      2. 6.6.2 Spy-Bi-Wire Interface
    7. 6.7  FRAM
    8. 6.8  RAM
    9. 6.9  Tiny RAM
    10. 6.10 Memory Protection Unit (MPU) Including IP Encapsulation
    11. 6.11 Peripherals
      1. 6.11.1  Digital I/O
      2. 6.11.2  Oscillator and Clock System (CS)
      3. 6.11.3  Power-Management Module (PMM)
      4. 6.11.4  Hardware Multiplier
      5. 6.11.5  Real-Time Clock (RTC_C)
      6. 6.11.6  Watchdog Timer (WDT_A)
      7. 6.11.7  System Module (SYS)
      8. 6.11.8  DMA Controller
      9. 6.11.9  Enhanced Universal Serial Communication Interface (eUSCI)
      10. 6.11.10 Timer_A TA0, Timer_A TA1
      11. 6.11.11 Timer_A TA2
      12. 6.11.12 Timer_A TA3
      13. 6.11.13 Timer_B TB0
      14. 6.11.14 ADC12_B
      15. 6.11.15 Comparator_E
      16. 6.11.16 CRC16
      17. 6.11.17 CRC32
      18. 6.11.18 AES256 Accelerator
      19. 6.11.19 True Random Seed
      20. 6.11.20 Shared Reference (REF_A)
      21. 6.11.21 LCD_C
      22. 6.11.22 Embedded Emulation
        1. 6.11.22.1 Embedded Emulation Module (EEM)
        2. 6.11.22.2 EnergyTrace++ Technology
      23. 6.11.23 Input/Output Diagrams
        1. 6.11.23.1  Digital I/O Functionality Port P1 to P7 and P9
        2. 6.11.23.2  Capacitive Touch Functionality on Port P1 to P7, P9, and PJ
        3. 6.11.23.3  Port P1 (P1.0 to P1.3) Input/Output With Schmitt Trigger
        4. 6.11.23.4  Port P1 (P1.4 to P1.7) Input/Output With Schmitt Trigger
        5. 6.11.23.5  Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger
        6. 6.11.23.6  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
        7. 6.11.23.7  Port P4 (P4.2 to P4.7) Input/Output With Schmitt Trigger
        8. 6.11.23.8  Port P5 (P5.4 to P5.7) Input/Output With Schmitt Trigger
        9. 6.11.23.9  Port P6 (P6.0 to P6.6) Input/Output With Schmitt Trigger
        10. 6.11.23.10 Port P7 (P7.0 to P7.4) Input/Output With Schmitt Trigger
        11. 6.11.23.11 Port P9 (P9.4 to P9.7) Input/Output With Schmitt Trigger
        12. 6.11.23.12 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
        13. 6.11.23.13 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
        14. 6.11.23.14 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
    12. 6.12 Device Descriptors (TLV)
    13. 6.13 Memory
      1. 6.13.1 Peripheral File Map
    14. 6.14 Identification
      1. 6.14.1 Revision Identification
      2. 6.14.2 Device Identification
      3. 6.14.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG
      4. 7.1.4 Reset
      5. 7.1.5 Unused Pins
      6. 7.1.6 General Layout Recommendations
      7. 7.1.7 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC12_B Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Detailed Design Procedure
        4. 7.2.1.4 Layout Guidelines
      2. 7.2.2 LCD_C Peripheral
        1. 7.2.2.1 Partial Schematic
        2. 7.2.2.2 Design Requirements
        3. 7.2.2.3 Detailed Design Procedure
        4. 7.2.2.4 Layout Guidelines
  8. 8Device and Documentation Support
    1. 8.1  Getting Started and Next Steps
    2. 8.2  Device Nomenclature
    3. 8.3  Tools and Software
    4. 8.4  Documentation Support
    5. 8.5  Related Links
    6. 8.6  Community Resources
    7. 8.7  Trademarks
    8. 8.8  Electrostatic Discharge Caution
    9. 8.9  Export Control Notice
    10. 8.10 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pin Attributes

Table 4-1 lists the attributes of each pin.

Table 4-1 Pin Attributes

FR692x(1), FR682x(1) FR697x(1), FR687x(1) SIGNAL NAME(1)(4)(5) SIGNAL TYPE(2) BUFFER TYPE(3) POWER SOURCE RESET STATE AFTER BOR(6)
PM, RGC DGG PM, RGC
PIN NO. LCD SEG PIN NO. LCD SEG PIN NO. LCD SEG
1 1 S4 P4.3 (RD) I/O LVCMOS DVCC OFF
UCA0SOMI I/O LVCMOS DVCC
UCA0RXD I LVCMOS DVCC
UCB1STE I/O LVCMOS DVCC
Sz O Analog DVCC
2 S3 7 S3 2 S3 P1.4 (RD) I/O LVCMOS DVCC OFF
UCB0CLK I/O LVCMOS DVCC
UCA0STE I/O LVCMOS DVCC
TA1.0 I/O LVCMOS DVCC
Sz O Analog DVCC
3 S2 8 S2 3 S2 P1.5 (RD) I/O LVCMOS DVCC OFF
UCB0STE I/O LVCMOS DVCC
UCA0CLK I/O LVCMOS DVCC
TA0.0 I/O LVCMOS DVCC
Sz O Analog DVCC
4 S1 9 S1 4 S1 P1.6 (RD) I/O LVCMOS DVCC OFF
UCB0SIMO I/O LVCMOS DVCC
UCB0SDA I/O LVCMOS DVCC
BSL_DAT I LVCMOS DVCC
TA0.1 I/O LVCMOS DVCC
Sz O Analog DVCC
5 S0 10 S0 5 S0 P1.7 (RD) I/O LVCMOS DVCC OFF
UCB0SOMI I/O LVCMOS DVCC
UCB0SCL I/O LVCMOS DVCC
BSL_CLK I LVCMOS DVCC
TA0.2 I/O LVCMOS DVCC
Sz O Analog DVCC
6 11 6 R33 I/O Analog DVCC
LCDCAP I/O Analog DVCC
7 12 7 P6.0 (RD) I/O LVCMOS DVCC OFF
R23 I/O Analog DVCC
8 13 8 P6.1 (RD) I/O LVCMOS DVCC OFF
R13 I/O Analog DVCC
LCDREF I Analog
9 14 9 P6.2 (RD) I/O LVCMOS DVCC OFF
COUT O LVCMOS DVCC
R03 I/O Analog DVCC
10 15 10 P6.3 (RD) I/O LVCMOS DVCC OFF
COM0 O Analog DVCC
11 S31 16 S27 11 S30 P6.4 (RD) I/O LVCMOS DVCC OFF
TB0.0 I/O LVCMOS DVCC
COM1 O Analog DVCC
Sz O Analog DVCC
12 S30 17 S26 12 S29 P6.5 (RD) I/O LVCMOS DVCC OFF
TB0.1 I/O LVCMOS DVCC
COM2 O Analog DVCC
Sz O Analog DVCC
13 S29 18 S25 13 S28 P6.6 (RD) I/O LVCMOS DVCC OFF
TB0.2 I/O LVCMOS DVCC
COM3 O Analog DVCC
Sz O Analog DVCC
14 S28 19 S24 14 S27 P3.0 (RD) I/O LVCMOS DVCC OFF
UCB1CLK I/O LVCMOS DVCC
TA3.2 I/O LVCMOS DVCC
Sz O Analog DVCC
15 S27 20 S23 15 S26 P3.1 (RD) I/O LVCMOS DVCC OFF
UCB1SIMO I/O LVCMOS DVCC
UCB1SDA I/O LVCMOS DVCC
TA3.3 I/O LVCMOS DVCC
Sz O Analog DVCC
16 S26 21 S22 16 S25 P3.2 (RD) I/O LVCMOS DVCC OFF
UCB1SOMI I/O LVCMOS DVCC
UCB1SCL I/O LVCMOS DVCC
TA3.4 I/O LVCMOS DVCC
Sz O Analog DVCC
17 17 DVSS1 P Power N/A
18 18 DVCC1 P Power N/A
19 22 19 TEST I LVCMOS DVCC OFF
SBWTCK I LVCMOS DVCC
20 23 20 RST I LVCMOS DVCC OFF
NMI I LVCMOS DVCC
SBWTDIO I/O LVCMOS DVCC
21 24 21 PJ.0 (RD) I/O LVCMOS DVCC OFF
TDO O LVCMOS DVCC
TB0OUTH I LVCMOS DVCC
SMCLK O LVCMOS DVCC
SRSCG1 O LVCMOS DVCC
22 25 22 PJ.1 (RD) I/O LVCMOS DVCC OFF
TDI I LVCMOS DVCC
TCLK I LVCMOS DVCC
MCLK O LVCMOS DVCC
SRSCG0 O LVCMOS DVCC
23 26 23 PJ.2 (RD) I/O LVCMOS DVCC OFF
TMS I LVCMOS DVCC
ACLK O LVCMOS DVCC
SROSCOFF O LVCMOS DVCC
24 27 24 PJ.3 (RD) I/O LVCMOS DVCC OFF
TCK I LVCMOS DVCC
COUT O LVCMOS DVCC
SRCPUOFF O LVCMOS DVCC
25 S25 28 S21 25 S24 P3.3 (RD) I/O LVCMOS DVCC OFF
TA1.1 I/O LVCMOS DVCC
TB0CLK I LVCMOS DVCC
Sz O Analog DVCC
26 S24 29 S20 26 S23 P3.4 (RD) I/O LVCMOS DVCC OFF
UCA1SIMO I/O LVCMOS DVCC
UCA1TXD O LVCMOS DVCC
TB0.0 I/O LVCMOS DVCC
Sz O Analog DVCC
27 S23 30 S19 27 S22 P3.5 (RD) I/O LVCMOS DVCC OFF
UCA1SOMI I/O LVCMOS DVCC
UCA1RXD I LVCMOS DVCC
TB0.1 I/O LVCMOS DVCC
Sz O Analog DVCC
28 S22 31 S18 28 S21 P3.6 (RD) I/O LVCMOS DVCC OFF
UCA1CLK I/O LVCMOS DVCC
TB0.2 I/O LVCMOS DVCC
Sz O Analog DVCC
29 S21 32 S17 29 S20 P3.7 (RD) I/O LVCMOS DVCC OFF
UCA1STE I/O LVCMOS DVCC
TB0.3 I/O LVCMOS DVCC
Sz O Analog DVCC
30 S20 33 S16 30 S19 P2.3 (RD) I/O LVCMOS DVCC OFF
UCA0STE I/O LVCMOS DVCC
TB0OUTH I LVCMOS DVCC
Sz O Analog DVCC
31 S19 34 S15 31 S18 P2.2 (RD) I/O LVCMOS DVCC OFF
UCA0CLK I/O LVCMOS DVCC
TB0.4 I/O LVCMOS DVCC
RTCCLK O LVCMOS DVCC
Sz O Analog DVCC
32 S18 35 S14 32 S17 P2.1 (RD) I/O LVCMOS DVCC OFF
UCA0SOMI I/O LVCMOS DVCC
UCA0RXD I LVCMOS DVCC
BSL_RX I LVCMOS DVCC
TB0.5 I/O LVCMOS DVCC
DMAE0 I LVCMOS DVCC
Sz O Analog DVCC
33 S17 36 S13 33 S16 P2.0 (RD) I/O LVCMOS DVCC OFF
UCA0SIMO I/O LVCMOS DVCC
UCA0TXD O LVCMOS DVCC
BSL_TX O LVCMOS DVCC
TB0.6 I/O LVCMOS DVCC
TB0CLK I LVCMOS DVCC
Sz O Analog DVCC
34 S16 37 S12 34 S15 P7.0 (RD) I/O LVCMOS DVCC OFF
TA0CLK I LVCMOS DVCC
Sz O Analog DVCC
35 S15 38 S11 35 S14 P7.1 (RD) I/O LVCMOS DVCC OFF
TA0.0 I/O LVCMOS DVCC
ACLK O LVCMOS DVCC
Sz O Analog DVCC
36 S14 39 S10 36 S13 P7.2 (RD) I/O LVCMOS DVCC OFF
TA0.1 I/O LVCMOS DVCC
Sz O Analog DVCC
37 S13 40 S9 37 S12 P7.3 (RD) I/O LVCMOS DVCC OFF
TA0.2 I/O LVCMOS DVCC
Sz O Analog DVCC
38 S12 41 S8 38 S11 P7.4 (RD) I/O LVCMOS DVCC OFF
SMCLK O LVCMOS DVCC
Sz O Analog DVCC
39 42 39 DVSS2 P Power N/A
40 43 40 DVCC2 P Power N/A
41 44 41 P1.3 (RD) I/O LVCMOS DVCC OFF
TA1.2 I/O LVCMOS DVCC
A3 I Analog AVCC
C3 I Analog AVCC
42 45 42 P1.2 (RD) I/O LVCMOS DVCC OFF
TA1.1 I/O LVCMOS DVCC
TA0CLK I LVCMOS DVCC
COUT O LVCMOS DVCC
A2 I Analog AVCC
C2 I Analog AVCC
43 46 43 P1.1 (RD) I/O LVCMOS DVCC OFF
TA0.2 I/O LVCMOS DVCC
TA1CLK I LVCMOS DVCC
COUT O LVCMOS DVCC
A1 I Analog AVCC
C1 I Analog AVCC
VREF+ O Analog AVCC
VeREF+ I Analog
44 47 44 P1.0 (RD) I/O LVCMOS DVCC OFF
TA0.1 I/O LVCMOS DVCC
DMAE0 I LVCMOS DVCC
RTCCLK O LVCMOS DVCC
A0 I Analog AVCC
C0 I Analog AVCC
VREF- O Analog AVCC
VeREF- I Analog
45 48 45 P9.4 (RD) I/O LVCMOS DVCC OFF
A12 I Analog AVCC
C12 I Analog AVCC
46 49 46 P9.5 (RD) I/O LVCMOS DVCC OFF
A13 I Analog AVCC
C13 I Analog AVCC
47 50 47 P9.6 (RD) I/O LVCMOS DVCC OFF
A14 I Analog AVCC
C14 I Analog AVCC
48 51 48 P9.7 (RD) I/O LVCMOS DVCC OFF
A15 I Analog AVCC
C15 I Analog AVCC
49 52 49 AVCC1 P Power N/A
50 53 50 AVSS1 P Power N/A
51 54 51 PJ.4 (RD) I/O LVCMOS DVCC OFF
LFXIN I Analog AVCC
52 55 52 PJ.5 (RD) I/O LVCMOS DVCC OFF
LFXOUT O Analog AVCC
53 56 53 AVSS2 P Power N/A
54 PJ.7 (RD) I/O LVCMOS DVCC OFF
HFXOUT O Analog AVCC
55 PJ.6 (RD) I/O LVCMOS DVCC OFF
HFXIN I Analog AVCC
56 AVSS3 P Power N/A
54 S11 P5.4 (RD) I/O LVCMOS DVCC OFF
UCA1SIMO I/O LVCMOS DVCC
UCA1TXD O LVCMOS DVCC
Sz O Analog DVCC
55 S10 P5.5 (RD) I/O LVCMOS DVCC OFF
UCA1SOMI I/O LVCMOS DVCC
UCA1RXD I LVCMOS DVCC
Sz O Analog DVCC
56 S9 P5.6 (RD) I/O LVCMOS DVCC OFF
UCA1CLK I/O LVCMOS DVCC
Sz O Analog DVCC
57 S8 57 S10 P5.7 (RD) I/O LVCMOS DVCC OFF
UCA1STE I/O LVCMOS DVCC
TB0CLK I LVCMOS DVCC
Sz O Analog DVCC
58 S7 1 S7 58 S9 P4.4 (RD) I/O LVCMOS DVCC OFF
UCB1STE I/O LVCMOS DVCC
TA1CLK I LVCMOS DVCC
Sz O Analog DVCC
59 S6 2 S6 59 S8 P4.5 (RD) I/O LVCMOS DVCC OFF
UCB1CLK I/O LVCMOS DVCC
TA1.0 I/O LVCMOS DVCC
Sz O Analog DVCC
60 S5 3 S5 60 S7 P4.6 (RD) I/O LVCMOS DVCC OFF
UCB1SIMO I/O LVCMOS DVCC
UCB1SDA I/O LVCMOS DVCC
TA1.1 I/O LVCMOS DVCC
Sz O Analog DVCC
61 S4 4 S4 61 S6 P4.7 (RD) I/O LVCMOS DVCC OFF
UCB1SOMI I/O LVCMOS DVCC
UCB1SCL I/O LVCMOS DVCC
TA1.2 I/O LVCMOS DVCC
Sz O Analog DVCC
62 5 62 DVSS3 P Power N/A
63 6 63 DVCC3 P Power N/A
64 64 S5 P4.2 (RD) I/O LVCMOS DVCC OFF
UCA0SIMO I/O LVCMOS DVCC
UCA0TXD O LVCMOS DVCC
UCB1CLK I/O LVCMOS DVCC
Sz O Analog DVCC
Signals names with (RD) denote the reset default pin name.
Signal Types: I = Input, O = Output, I/O = Input or Output.
Buffer Types: LVCMOS, Analog, or Power (see Table 4-3 for details)
To determine the pin mux encodings for each pin, see the Port I/O Diagrams section.
Sz = The LCD segment that is assigned to each pin can vary by package – see the "LCD SEG" columns for the assignment on this pin.
Reset States:
OFF = High impedance with Schmitt-trigger inputs and pullup or pulldown (if available) disabled
N/A = Not applicable