SLAS887A September   2014  – May 2018

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
    3. 4.3 Pin Multiplexing
    4. 4.4 Connection of Unused Pins
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Active Mode Supply Current (Into VCC) Excluding External Current
    5. 5.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6 Thermal Resistance Characteristics
    7. 5.7 Timing and Switching Characteristics
      1. 5.7.1  Reset Timing
        1. Table 5-1 Reset Timing
      2. 5.7.2  Clock Specifications
        1. Table 5-2 DCO in External Resistor Mode
        2. Table 5-3 DCO in Internal Resistor Mode
        3. Table 5-4 DCO Overall Tolerance Table
        4. Table 5-5 DCO in Bypass Mode Recommended Operating Conditions
      3. 5.7.3  Wake-up Characteristics
        1. Table 5-6 Wake-up Times From Low Power Modes
      4. 5.7.4  I/O Ports
        1. Table 5-7   Schmitt-Trigger Inputs – General-Purpose I/O
        2. Table 5-8   Inputs – Ports P1 and P2
        3. Table 5-9   Leakage Current – General-Purpose I/O
        4. Table 5-10 Outputs – General-Purpose I/O
        5. Table 5-11 Output Frequency – General-Purpose I/O
        6. 5.7.4.1     Typical Characteristics – Outputs
      5. 5.7.5  Power Management Module
        1. Table 5-12 PMM, High-Side Brownout Reset (BORH)
        2. Table 5-13 PMM, Low-Side SVS (SVSL)
        3. Table 5-14 PMM, Core Voltage
        4. Table 5-15 PMM, Voltage Monitor (VMON)
      6. 5.7.6  Reference Module
        1. Table 5-16 Voltage Reference (REF)
        2. Table 5-17 Temperature Sensor
      7. 5.7.7  SD24
        1. Table 5-18 SD24 Power Supply and Recommended Operating Conditions
        2. Table 5-19 SD24 Internal Voltage Reference
        3. Table 5-20 SD24 External Voltage Reference
        4. Table 5-21 SD24 Input Range
        5. Table 5-22 SD24 Performance, Internal Reference (SD24REFS = 1, SD24OSRx = 256)
        6. Table 5-23 SD24 Performance, External Reference (SD24REFS = 0, SD24OSRx = 256)
      8. 5.7.8  eUSCI
        1. Table 5-24 eUSCI (UART Mode) Recommended Operating Conditions
        2. Table 5-25 eUSCI (UART Mode)
        3. Table 5-26 eUSCI (SPI Master Mode) Recommended Operating Conditions
        4. Table 5-27 eUSCI (SPI Master Mode)
        5. Table 5-28 eUSCI (SPI Slave Mode)
        6. Table 5-29 eUSCI (I2C Mode)
      9. 5.7.9  Timer_A
        1. Table 5-30 Timer_A
      10. 5.7.10 Flash
        1. Table 5-31 Flash Memory
      11. 5.7.11 Emulation and Debug
        1. Table 5-32 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  Functional Block Diagrams
    3. 6.3  CPU
    4. 6.4  Instruction Set
    5. 6.5  Operating Modes
    6. 6.6  Interrupt Vector Addresses
    7. 6.7  Special Function Registers
      1. Table 6-4 Interrupt Enable 1 (Address = 00h)
      2. Table 6-5 Interrupt Flag Register 1 (Address = 02h)
    8. 6.8  Flash Memory
    9. 6.9  JTAG Operation
      1. 6.9.1 JTAG Standard Interface
      2. 6.9.2 Spy-Bi-Wire Interface
      3. 6.9.3 JTAG Disable Register
        1. Table 6-1 SYSJTAGDIS Register
    10. 6.10 Peripherals
      1. 6.10.1 Clock System
      2. 6.10.2 Power-Management Module (PMM)
      3. 6.10.3 Digital I/O
      4. 6.10.4 Watchdog Timer (WDT)
      5. 6.10.5 Timer TA0
      6. 6.10.6 Timer TA1
      7. 6.10.7 Enhanced Universal Serial Communication Interface (eUSCI)
      8. 6.10.8 Hardware Multiplier
      9. 6.10.9 SD24
    11. 6.11 Input/Output Diagrams
      1. 6.11.1 Port P1, P1.0 to P1.3, Input/Output With Schmitt Trigger
      2. 6.11.2 Port P1, P1.4 to P1.7, Input/Output With Schmitt Trigger
      3. 6.11.3 Port P2, P2.0 to P2.2 and P2.4 to P2.7, Input/Output With Schmitt Trigger
      4. 6.11.4 Port P2, P2.3, Input/Output With Schmitt Trigger
    12. 6.12 Device Descriptor
    13. 6.13 Memory
      1. 6.13.1 Peripheral File Map
    14. 6.14 Identification
      1. 6.14.1 Device Identification
      2. 6.14.2 JTAG Identification
  7. 7Applications, Implementation, and Layout
  8. 8Device and Documentation Support
    1. 8.1 Getting Started and Next Steps
    2. 8.2 Device Nomenclature
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Related Links
    6. 8.6 Community Resources
    7. 8.7 Trademarks
    8. 8.8 Electrostatic Discharge Caution
    9. 8.9 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Peripheral File Map

Table 6-16 lists the peripherals that support word access, and Table 6-17 lists the peripherals that support byte access. Peripherals that support both access types are listed in both tables.

Table 6-16 Peripherals With Word Access

MODULE REGISTER DESCRIPTION ACRONYM ADDRESS
SYS JTAG disable register SYSJTAGDIS 0x01FE
Timer TA1 Capture/compare register 2 TA1CCR2 0x0196
Capture/compare register 1 TA1CCR1 0x0194
Capture/compare register 0 TA1CCR0 0x0192
Timer_A register TA1R 0x0190
Capture/compare control 2 TA1CCTL2 0x0186
Capture/compare control 1 TA1CCTL1 0x0184
Capture/compare control 0 TA1CCTL0 0x0182
Timer_A control TA1CTL 0x0180
Timer_A interrupt vector TA1IV 0x011E
Timer TA0 Capture/compare register 2 TA0CCR2 0x0176
Capture/compare register 1 TA0CCR1 0x0174
Capture/compare register 0 TA0CCR0 0x0172
Timer_A register TA0R 0x0170
Capture/compare control 2 TA0CCTL2 0x0166
Capture/compare control 1 TA0CCTL1 0x0164
Capture/compare control 0 TA0CCTL0 0x0162
Timer_A control TA0CTL 0x0160
Timer_A interrupt vector TA0IV 0x012E
eUSCI_A0 USCI_A control word 0 UCA0CTLW0 0x0140
USCI _A control word 1 UCA0CTLW1 0x0142
USCI_A baud rate 0 UCA0BR0 0x0146
USCI_A baud rate 1 UCA0BR1 0x0147
USCI_A modulation control UCA0MCTLW 0x0148
USCI_A status UCA0STAT 0x014A
USCI_A receive buffer UCA0RXBUF 0x014C
USCI_A transmit buffer UCA0TXBUF 0x014E
USCI_A LIN control UCA0ABCTL 0x0150
USCI_A IrDA transmit control UCA0IRTCTL 0x0152
USCI_A IrDA receive control UCA0IRRCTL 0x0153
USCI_A interrupt enable UCA0IE 0x015A
USCI_A interrupt flags UCA0IFG 0x015C
USCI_A interrupt vector word UCA0IV 0x015E
eUSCI_B0 USCI_B control word 0 UCB0CTLW0 0x01C0
USCI_B control word 1 UCB0CTLW1 0x01C2
USCI_B bit rate 0 UCB0BR0 0x01C6
USCI_B bit rate 1 UCB0BR1 0x01C7
USCI_B status word UCB0STATW 0x01C8
USCI_B byte counter threshold UCB0TBCNT 0x01CA
USCI_B receive buffer UCB0RXBUF 0x01CC
USCI_B transmit buffer UCB0TXBUF 0x01CE
USCI_B I2C own address 0 UCB0I2COA0 0x01D4
USCI_B I2C own address 1 UCB0I2COA1 0x01D6
USCI_B I2C own address 2 UCB0I2COA2 0x01D8
USCI_B I2C own address 3 UCB0I2COA3 0x01DA
USCI_B received address UCB0ADDRX 0x01DC
USCI_B address mask UCB0ADDMASK 0x01DE
USCI I2C slave address UCB0I2CSA 0x01E0
USCI interrupt enable UCB0IE 0x01EA
USCI interrupt flags UCB0IFG 0x01EC
USCI interrupt vector word UCB0IV 0x01EE
Hardware Multiplier Sum extend SUMEXT 0x013E
Result high word RESHI 0x013C
Result low word RESLO 0x013A
Second operand OP2 0x0138
Multiply signed + accumulate/operand 1 MACS 0x0136
Multiply + accumulate/operand 1 MAC 0x0134
Multiply signed/operand 1 MPYS 0x0132
Multiply unsigned/operand 1 MPY 0x0130
Flash Memory Flash control 3 FCTL3 0x012C
Flash control 2 FCTL2 0x012A
Flash control 1 FCTL1 0x0128
Watchdog Timer Watchdog/timer control WDTCTL 0x0120
SD24
(Also see Table 6-17)
SD24 interrupt vector word register SD24IV 0x01F0
Channel 3 conversion memory(1)(2) SD24MEM3 0x0116
Channel 2 conversion memory(2) SD24MEM2 0x0114
Channel 1 conversion memory SD24MEM1 0x0112
Channel 0 conversion memory SD24MEM0 0x0110
Channel 3 control(1)(2) SD24CCTL3 0x0108
Channel 2 control(2) SD24CCTL2 0x0106
Channel 1 control SD24CCTL1 0x0104
Channel 0 control SD24CCTL0 0x0102
General Control SD24CTL 0x0100
Not available on MSP430i2031 and MSP430i2030 devices.
Not available on MSP430i2021 and MSP430i2020 devices.

Table 6-17 Peripherals With Byte Access

MODULE REGISTER DESCRIPTION REGISTER NAME ADDRESS
SD24
(Also see Table 6-16)
SD24 trim SD24TRIM 0x00BF
Channel 3 preload(1)(2) SD24PRE3 0x00BB
Channel 2 preload(2) SD24PRE2 0x00BA
Channel 1 preload SD24PRE1 0x00B9
Channel 0 preload SD24PRE0 0x00B8
Channel 3 input control(1)(2) SD24INCTL3 0x00B3
Channel 2 input control(2) SD24INCTL2 0x00B2
Channel 1 input control SD24INCTL1 0x00B1
Channel 0 input control SD24INCTL0 0x00B0
PMM Reference calibration 1 REFCAL1 0x0063
Reference calibration 0 REFCAL0 0x0062
Voltage monitor control VMONCTL 0x0061
LPM4.5 control LPM45CTL 0x0060
Clock System Clock system external resistor temperature calibration CSERTCAL 0x0055
Clock system external resistor frequency calibration CSERFCAL 0x0054
Clock system internal resistor temperature calibration CSIRTCAL 0x0053
Clock system internal resistor frequency calibration CSIRFCAL 0x0052
Clock system control 1 CSCTL1 0x0051
Clock system control 0 CSCTL0 0x0050
Port P2 Port P2 interrupt flag P2IFG 0x002D
Port P2 interrupt enable P2IE 0x002B
Port P2 interrupt edge select P2IES 0x0029
Port P2 interrupt vector word P2IV 0x002E
Port P2 selection 1 P2SEL1 0x001D
Port P2 selection 0 P2SEL0 0x001B
Port P2 direction P2DIR 0x0015
Port P2 output P2OUT 0x0013
Port P2 input P2IN 0x0011
Port P1 Port P1 interrupt flag P1IFG 0x002C
Port P1 interrupt enable P1IE 0x002A
Port P1 interrupt edge select P1IES 0x0028
Port P1 interrupt vector word P1IV 0x001E
Port P1 selection 1 P1SEL1 0x001C
Port P1 selection 0 P1SEL0 0x001A
Port P1 direction P1DIR 0x0014
Port P1 output P1OUT 0x0012
Port P1 input P1IN 0x0010
Special Function SFR interrupt flag 1 IFG1 0x0002
SFR interrupt enable 1 IE1 0x0000
Not available on MSP430i2031 or MSP430i2030 devices.
Not available on MSP430i2021 or MSP430i2020 devices.