SLAS887B
September 2014 – March 2020
PRODUCTION DATA.
1
Device Overview
1.1
Features
1.2
Applications
1.3
Description
1.4
Functional Block Diagram
2
Revision History
3
Device Comparison
3.1
Related Products
4
Terminal Configuration and Functions
4.1
Pin Diagrams
4.2
Signal Descriptions
Table 4-1
Signal Descriptions
4.3
Pin Multiplexing
4.4
Connection of Unused Pins
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Active Mode Supply Current (Into VCC) Excluding External Current
5.5
Low-Power Mode Supply Currents (Into VCC) Excluding External Current
5.6
Thermal Resistance Characteristics
5.7
Timing and Switching Characteristics
5.7.1
Reset Timing
Table 5-1
Reset Timing
5.7.2
Clock Specifications
Table 5-2
DCO in External Resistor Mode
Table 5-3
DCO in Internal Resistor Mode
Table 5-4
DCO Overall Tolerance Table
Table 5-5
DCO in Bypass Mode Recommended Operating Conditions
5.7.3
Wake-up Characteristics
Table 5-6
Wake-up Times From Low Power Modes
5.7.4
I/O Ports
Table 5-7
Schmitt-Trigger Inputs – General-Purpose I/O
Table 5-8
Inputs – Ports P1 and P2
Table 5-9
Leakage Current – General-Purpose I/O
Table 5-10
Outputs – General-Purpose I/O
Table 5-11
Output Frequency – General-Purpose I/O
5.7.4.1
Typical Characteristics – Outputs
5.7.5
Power Management Module
Table 5-12
PMM, High-Side Brownout Reset (BORH)
Table 5-13
PMM, Low-Side SVS (SVSL)
Table 5-14
PMM, Core Voltage
Table 5-15
PMM, Voltage Monitor (VMON)
5.7.6
Reference Module
Table 5-16
Voltage Reference (REF)
Table 5-17
Temperature Sensor
5.7.7
SD24
Table 5-18
SD24 Power Supply and Recommended Operating Conditions
Table 5-19
SD24 Internal Voltage Reference
Table 5-20
SD24 External Voltage Reference
Table 5-21
SD24 Input Range
Table 5-22
SD24 Performance, Internal Reference (SD24REFS = 1, SD24OSRx = 256)
Table 5-23
SD24 Performance, External Reference (SD24REFS = 0, SD24OSRx = 256)
5.7.8
eUSCI
Table 5-24
eUSCI (UART Mode) Clock Frequency
Table 5-25
eUSCI (UART Mode) Deglitch Characteristics
Table 5-26
eUSCI (SPI Master Mode) Clock Frequency
Table 5-27
eUSCI (SPI Master Mode) Timing
Table 5-28
eUSCI (SPI Slave Mode) Timing
Table 5-29
eUSCI (I2C Mode) Timing
5.7.9
Timer_A
Table 5-30
Timer_A
5.7.10
Flash
Table 5-31
Flash Memory
5.7.11
Emulation and Debug
Table 5-32
JTAG and Spy-Bi-Wire Interface
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagrams
6.3
CPU
6.4
Instruction Set
6.5
Operating Modes
6.6
Interrupt Vector Addresses
6.7
Special Function Registers
Table 6-4
Interrupt Enable 1 (Address = 00h)
Table 6-5
Interrupt Flag Register 1 (Address = 02h)
6.8
Flash Memory
6.9
JTAG Operation
6.9.1
JTAG Standard Interface
6.9.2
Spy-Bi-Wire Interface
6.9.3
JTAG Disable Register
Table 6-1
SYSJTAGDIS Register
6.10
Peripherals
6.10.1
Clock System
6.10.2
Power-Management Module (PMM)
6.10.3
Digital I/O
6.10.4
Watchdog Timer (WDT)
6.10.5
Timer TA0
6.10.6
Timer TA1
6.10.7
Enhanced Universal Serial Communication Interface (eUSCI)
6.10.8
Hardware Multiplier
6.10.9
SD24
6.11
Input/Output Diagrams
6.11.1
Port P1, P1.0 to P1.3, Input/Output With Schmitt Trigger
6.11.2
Port P1, P1.4 to P1.7, Input/Output With Schmitt Trigger
6.11.3
Port P2, P2.0 to P2.2 and P2.4 to P2.7, Input/Output With Schmitt Trigger
6.11.4
Port P2, P2.3, Input/Output With Schmitt Trigger
6.12
Device Descriptor
6.13
Memory
6.13.1
Peripheral File Map
6.14
Identification
6.14.1
Device Identification
6.14.2
JTAG Identification
7
Applications, Implementation, and Layout
8
Device and Documentation Support
8.1
Getting Started and Next Steps
8.2
Device Nomenclature
8.3
Tools and Software
8.4
Documentation Support
8.5
Related Links
8.6
Support Resources
8.7
Trademarks
8.8
Electrostatic Discharge Caution
8.9
Glossary
9
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
PW|28
MPDS364
RHB|32
MPQF130D
Thermal pad, mechanical data (Package|Pins)
PW|28
QFND466A
RHB|32
QFND257K
Orderable Information
slas887b_oa
slas887b_pm
5.7.7
SD24