SLASEK6 October   2017 MSP432E411Y

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Characteristics
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. Table 4-3 Signal Descriptions
    4. 4.4 GPIO Pin Multiplexing
    5. 4.5 Buffer Type
    6. 4.6 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Recommended DC Operating Conditions
    5. 5.5  Recommended GPIO Operating Characteristics
    6. 5.6  Recommended Fast GPIO Pad Operating Conditions
    7. 5.7  Recommended Slow GPIO Pad Operating Conditions
    8. 5.8  GPIO Current Restrictions
    9. 5.9  I/O Reliability
    10. 5.10 Current Consumption
    11. 5.11 Peripheral Current Consumption
    12. 5.12 LDO Regulator Characteristics
    13. 5.13 Power Dissipation
    14. 5.14 Thermal Resistance Characteristics, 212-Pin ZAD (NFBGA) Package
    15. 5.15 Timing and Switching Characteristics
      1. 5.15.1  Load Conditions
      2. 5.15.2  Power Supply Sequencing
        1. 5.15.2.1 Power and Brownout
          1. Table 5-3 Power and Brownout Levels
          2. 5.15.2.1.1 VDDA Levels
          3. 5.15.2.1.2 VDD Levels
          4. 5.15.2.1.3 VDDC Levels
          5. 5.15.2.1.4 VDD Glitch Response
          6. 5.15.2.1.5 VDD Droop Response
      3. 5.15.3  Reset Timing
        1. Table 5-4 Reset Characteristics
      4. 5.15.4  Clock Specifications
        1. 5.15.4.1 PLL Specifications
          1. Table 5-5 Phase Locked Loop (PLL) Characteristics
          2. 5.15.4.1.1 PLL Configuration
        2. 5.15.4.2 PIOSC Specifications
        3. 5.15.4.3 Low-Frequency Oscillator Specifications
          1. Table 5-9 Low-Frequency Oscillator Characteristics
        4. 5.15.4.4 Hibernation Low-Frequency Oscillator Specifications
          1. Table 5-10 Hibernation External Oscillator (XOSC) Input Characteristics
          2. Table 5-11 Hibernation Internal Low-Frequency Oscillator Clock Characteristics
        5. 5.15.4.5 Main Oscillator Specifications
          1. Table 5-12 Main Oscillator Input Characteristics
        6. 5.15.4.6 Main Oscillator Specification WIth ADC
          1. Table 5-14 System Clock Characteristics With ADC Operation
        7. 5.15.4.7 System Clock Characteristics With USB Operation
          1. Table 5-15 System Clock Characteristics With USB Operation
      5. 5.15.5  Sleep Modes
        1. Table 5-16 Wake From Sleep Characteristics
        2. Table 5-17 Wake From Deep Sleep Characteristics
      6. 5.15.6  Hibernation Module
        1. Table 5-18 Hibernation Module Battery Characteristics
        2. Table 5-19 Hibernation Module Characteristics
        3. Table 5-20 Hibernation Module Tamper I/O Characteristics
      7. 5.15.7  Flash Memory
        1. Table 5-21 Flash Memory Characteristics
      8. 5.15.8  EEPROM
        1. Table 5-22 EEPROM Characteristics
      9. 5.15.9  Input/Output Pin Characteristics
        1. Table 5-23 Fast GPIO Module Characteristics
        2. Table 5-24 Slow GPIO Module Characteristics
        3. 5.15.9.1    Types of I/O Pins and ESD Protection
          1. 5.15.9.1.1 Hibernate WAKE pin
            1. Table 5-25 Pad Voltage and Current Characteristics for Hibernate WAKE Pin
          2. 5.15.9.1.2 Nonpower I/O Pins
            1. Table 5-26 Nonpower I/O Pad Voltage and Current Characteristics
      10. 5.15.10 External Peripheral Interface (EPI)
        1. Table 5-28 EPI SDRAM Characteristics
        2. Table 5-29 EPI SDRAM Interface Characteristics
        3. Table 5-30 EPI Host-Bus 8 and Host-Bus 16 Interface Characteristics
        4. Table 5-31 EPI General-Purpose Interface Characteristics
        5. Table 5-32 EPI PSRAM Interface Characteristics
      11. 5.15.11 Analog-to-Digital Converter (ADC)
        1. Table 5-33 Electrical Characteristics for ADC at 1 Msps
        2. Table 5-34 Electrical Characteristics for ADC at 2 Msps
      12. 5.15.12 Synchronous Serial Interface (SSI)
        1. Table 5-35 SSI Characteristics
        2. Table 5-36 Bi- and Quad-SSI Characteristics
      13. 5.15.13 Inter-Integrated Circuit (I2C) Interface
        1. Table 5-37 I2C Characteristics
      14. 5.15.14 Ethernet Controller
        1. 5.15.14.1 DC Characteristics
          1. Table 5-38 Ethernet PHY DC Characteristics
        2. 5.15.14.2 Clock Characteristics for Ethernet
          1. Table 5-39 MOSC 25-MHz Crystal Specification
          2. Table 5-40 MOSC Single-Ended 25-MHz Oscillator Specification
          3. Table 5-41 EN0RREF_CLK 50-MHz Oscillator Specification
        3. 5.15.14.3 AC Characteristics
          1. Table 5-42 Ethernet Controller Enable and Software Reset Timing
          2. Table 5-43 MII Serial Management Timing
          3. Table 5-44 100-Mbps MII Transmit Timing
          4. Table 5-45 100-Mbps MII Receive Timing
          5. Table 5-46 100Base-TX Transmit Timing
          6. Table 5-47 10-Mbps MII Transmit Timing
          7. Table 5-48 10-Mbps MII Receive Timing
          8. Table 5-49 10Base-T Normal Link Pulse Timing
          9. Table 5-50 Auto-Negotiation Fast Link Pulse (FLP) Timing
          10. Table 5-51 100Base-TX Signal Detect Timing
          11. Table 5-52 RMII Transmit Timing
          12. Table 5-53 RMII Receive Timing
      15. 5.15.15 Universal Serial Bus (USB) Controller
        1. Table 5-54 ULPI Interface Timing
      16. 5.15.16 LCD Controller
        1. Table 5-55 LCD Controller Load Capacitance Limits
        2. 5.15.16.1   LCD Interface Display Driver (LIDD Mode)
          1. Table 5-56 LCD Switching Characteristics
          2. Table 5-57 Timing Requirements for LCDDATA in LIDD Mode
          3. 5.15.16.1.1 Hitachi Mode
          4. 5.15.16.1.2 Motorola 6800 Mode
          5. 5.15.16.1.3 Intel 8080 Mode
        3. 5.15.16.2   LCD Raster Mode
          1. Table 5-58 Switching Characteristics for LCD Raster Mode
      17. 5.15.17 Analog Comparator
        1. Table 5-59 Analog Comparator Characteristics
        2. Table 5-60 Analog Comparator Characteristics
        3. Table 5-61 Analog Comparator Voltage Reference Characteristics
        4. Table 5-62 Analog Comparator Voltage Reference Characteristics
      18. 5.15.18 Pulse-Width Modulator (PWM)
        1. Table 5-63 PWM Timing Characteristics
      19. 5.15.19 Emulation and Debug
        1. Table 5-64 JTAG Characteristics
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Arm Cortex-M4F Processor Core
      1. 6.3.1 Processor Core
      2. 6.3.2 System Timer (SysTick)
      3. 6.3.3 Nested Vectored Interrupt Controller (NVIC)
      4. 6.3.4 System Control Block (SCB)
      5. 6.3.5 Memory Protection Unit (MPU)
      6. 6.3.6 Floating-Point Unit (FPU)
    4. 6.4 On-Chip Memory
      1. 6.4.1 SRAM
      2. 6.4.2 Flash Memory
      3. 6.4.3 ROM
      4. 6.4.4 EEPROM
      5. 6.4.5 Memory Map
    5. 6.5 Peripherals
      1. 6.5.1  External Peripheral Interface (EPI)
      2. 6.5.2  Cyclical Redundancy Check (CRC)
      3. 6.5.3  Advanced Encryption Standard (AES) Accelerator
      4. 6.5.4  Data Encryption Standard (DES) Accelerator
      5. 6.5.5  Secure Hash Algorithm/Message Digest Algorithm (SHA/MD5) Accelerator
      6. 6.5.6  Serial Communications Peripherals
        1. 6.5.6.1 Ethernet MAC and PHY
        2. 6.5.6.2 Controller Area Network (CAN)
        3. 6.5.6.3 Universal Serial Bus (USB)
        4. 6.5.6.4 Universal Asynchronous Receiver/Transmitter (UART)
        5. 6.5.6.5 1-Wire Master Module
        6. 6.5.6.6 Inter-Integrated Circuit (I2C)
        7. 6.5.6.7 Quad Synchronous Serial Interface (QSSI)
      7. 6.5.7  System Integration
        1. 6.5.7.1 Direct Memory Access (DMA)
        2. 6.5.7.2 System Control and Clocks
        3. 6.5.7.3 Programmable Timers
        4. 6.5.7.4 Capture Compare PWM (CCP) Pins
        5. 6.5.7.5 Hibernation (HIB) Module
        6. 6.5.7.6 Watchdog Timers
        7. 6.5.7.7 Programmable GPIOs
      8. 6.5.8  LCD Controller
      9. 6.5.9  Advanced Motion Control
        1. 6.5.9.1 Pulse Width Modulation (PWM)
        2. 6.5.9.2 Quadrature Encoder With Index (QEI) Module
      10. 6.5.10 Analog
        1. 6.5.10.1 ADC
        2. 6.5.10.2 Analog Comparators
      11. 6.5.11 JTAG and Arm Serial Wire Debug
      12. 6.5.12 Peripheral Memory Map
    6. 6.6 Identification
    7. 6.7 Boot Modes
  7. 7Applications, Implementation, and Layout
    1. 7.1 System Design Guidelines
  8. 8Device and Documentation Support
    1. 8.1 Getting Started and Next Steps
    2. 8.2 Device Nomenclature
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Community Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Export Control Notice
    9. 8.9 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • ZAD|212
Thermal pad, mechanical data (Package|Pins)
Orderable Information

GPIO Pin Multiplexing

Table 4-4 describes the GPIO pins and alternate functions.

Table 4-4 GPIO Pins and Alternate Functions

I/OPINANALOG OR SPECIAL FUNCTION(1)DIGITAL FUNCTION (GPIOPCTL PMCx BIT FIELD ENCODING)
1234567811131415
PA0 V3 U0Rx I2C9SCL T0CCP0 CAN0Rx
PA1 W3 U0Tx I2C9SDA T0CCP1 CAN0Tx
PA2 T6 U4Rx I2C8SCL T1CCP0 SSI0Clk
PA3 U5 U4Tx I2C8SDA T1CCP1 SSI0Fss
PA4 V4 U3Rx I2C7SCL T2CCP0 SSI0XDAT0
PA5 W4 U3Tx I2C7SDA T2CCP1 SSI0XDAT1
PA6 V5 U2Rx I2C6SCL T3CCP0 USB0EPEN SSI0XDAT2 EN0RXCK EPI0S8
PA7 R7 U2Tx I2C6SDA T3CCP1 USB0PFLT USB0EPEN SSI0XDAT3 EPI0S9
PB0 A16 USB0ID U1Rx I2C5SCL T4CCP0 CAN1Rx
PB1 B16 USB0VBUS U1Tx I2C5SDA T4CCP1 CAN1Tx
PB2 A17 I2C0SCL T5CCP0 EN0MDC USB0STP EPI0S27
PB3 B17 I2C0SDA T5CCP1 EN0MDIO USB0CLK EPI0S28
PB4 C6 AIN10 U0CTS I2C5SCL SSI1Fss
PB5 B6 AIN11 U0RTS I2C5SDA SSI1Clk
PB6 F2 I2C6SCL T6CCP0
PB7 F1 I2C6SDA T6CCP1
PC0 B15 TCLK SWCLK
PC1 C15 TMS SWDIO
PC2 D14 TDI
PC3 C14 TDO SWO
PC4 M2 C1- U7Rx T7CCP0 EPI0S7
PC5 M1 C1+ U7Tx T7CCP1 EPI0S6
PC6 L2 C0+ U5Rx EPI0S5
PC7 K3 C0- U5Tx EPI0S4
PD0 C2 AIN15 I2C7SCL T0CCP0 C0o SSI2XDAT1
PD1 C1 AIN14 I2C7SDA T0CCP1 C1o SSI2XDAT0
PD2 D2 AIN13 I2C8SCL T1CCP0 C2o SSI2Fss
PD3 D1 AIN12 I2C8SDA T1CCP1 SSI2Clk
PD4 A4 AIN7 U2Rx T3CCP0 SSI1XDAT2
PD5 B4 AIN6 U2Tx T3CCP1 SSI1XDAT3
PD6 B3 AIN5 U2RTS T4CCP0 USB0EPEN SSI2XDAT3
PD7 B2 AIN4 U2CTS T4CCP1 USB0PFLT NMI SSI2XDAT2
PE0 H3 AIN3 U1RTS
PE1 H2 AIN2 U1DSR
PE2 G1 AIN1 U1DCD
PE3 G2 AIN0 U1DTR OWIRE
PE4 A5 AIN9 U1RI SSI1XDAT0
PE5 B5 AIN8 SSI1XDAT1
PE6 A7 AIN20 U0CTS I2C9SCL
PE7 B7 AIN21 U0RTS I2C9SDA NMI
PF0 U6 EN0LED0 M0PWM0 SSI3XDAT1 TRD2
PF1 V6 EN0LED2 M0PWM1 SSI3XDAT0 TRD1
PF2 W6 EN0MDC M0PWM2 SSI3Fss TRD0
PF3 T7 EN0MDIO M0PWM3 SSI3Clk TRCLK
PF4 V7 EN0LED1 M0FAULT0 SSI3XDAT2 TRD3
PF5 W7 SSI3XDAT3
PF6 T8 LCDMCLK
PF7 U8 LCDDATA02
PG0 N15 I2C1SCL EN0PPS M0PWM4 EPI0S11
PG1 T14 I2C1SDA M0PWM5 EPI0S10
PG2 V11 I2C2SCL EN0TXCK SSI2XDAT3
PG3 M16 I2C2SDA EN0TXEN SSI2XDAT2
PG4 K17 U0CTS I2C3SCL OWIRE EN0TXD0 SSI2XDAT1
PG5 K15 U0RTS I2C3SDA OWALT EN0TXD1 SSI2XDAT0
PG6 V12 I2C4SCL OWIRE EN0RXER SSI2Fss
PG7 U14 I2C4SDA OWIRE EN0RXDV SSI2Clk
PH0 P4 U0RTS EPI0S0
PH1 R2 U0CTS EPI0S1
PH2 R1 U0DCD EPI0S2
PH3 T1 U0DSR EPI0S3
PH4 R3 U0DTR
PH5 T2 U0RI EN0PPS
PH6 U2 U5Rx U7Rx
PH7 V2 U5Tx U7Tx
PJ0 C8 U3Rx EN0PPS
PJ1 E7 U3Tx
PJ2 H17 U2RTS LCDDATA14
PJ3 F16 U2CTS LCDDATA15
PJ4 F18 U3RTS LCDDATA16
PJ5 E17 U3CTS LCDDATA17
PJ6 N1 U4RTS LCDAC
PJ7 K5 U4CTS
PK0 J1 AIN16 U4Rx EPI0S0
PK1 J2 AIN17 U4Tx EPI0S1
PK2 K1 AIN18 U4RTS EPI0S2
PK3 K2 AIN19 U4CTS EPI0S3
PK4 U19 I2C3SCL EN0LED0 M0PWM6 EN0INTRN EN0RXD3 EPI0S32
PK5 V17 I2C3SDA EN0LED2 M0PWM7 EN0RXD2 EPI0S31
PK6 V16 I2C4SCL EN0LED1 M0FAULT1 EN0TXD2 EPI0S25
PK7 W16 U0RI I2C4SDA RTCCLK M0FAULT2 EN0TXD3 EPI0S24
PL0 G16 I2C2SDA M0FAULT3 USB0D0 EPI0S16
PL1 H19 I2C2SCL PhA0 USB0D1 EPI0S17
PL2 G18 C0o PhB0 USB0D2 EPI0S18
PL3 J18 C1o IDX0 USB0D3 EPI0S19
PL4 H18 T0CCP0 USB0D4 EPI0S26
PL5 G19 T0CCP1 USB0D5 EPI0S33
PL6 C18 USB0DP T1CCP0
PL7 B18 USB0DM T1CCP1
PM0 K18 T2CCP0 EPI0S15
PM1 K19 T2CCP1 EPI0S14
PM2 L18 T3CCP0 EPI0S13
PM3 L19 T3CCP1 EPI0S12
PM4 M18 TMPR3 U0CTS T4CCP0 EN0RREF_CLK
PM5 G15 TMPR2 U0DCD T4CCP1
PM6 N19 TMPR1 U0DSR T5CCP0 EN0CRS
PM7 N18 TMPR0 U0RI T5CCP1 EN0COL
PN0 C10 U1RTS
PN1 B11 U1CTS
PN2 A11 U1DCD U2RTS EPI0S29
PN3 B10 U1DSR U2CTS EPI0S30
PN4 A10 U1DTR U3RTS I2C2SDA EPI0S34
PN5 B9 U1RI U3CTS I2C2SCL EPI0S35
PN6 T12 U4RTS EN0TXER LCDDATA13
PN7 U12 U1RTS U4CTS LCDDATA12
PP0 D6 C2+ U6Rx T6CCP0 EN0INTRN SSI3XDAT2
PP1 D7 C2- U6Tx T6CCP1 SSI3XDAT3
PP2 B13 U0DTR USB0NXT EPI0S29
PP3 C12 U1CTS U0DCD RTCCLK USB0DIR EPI0S30
PP4 D8 U3RTS U0DSR OWIRE USB0D7
PP5 B12 U3CTS I2C2SCL OWALT USB0D6
PP6 B8 AIN23 U1DCD I2C2SDA
PP7 A8 AIN22 OWIRE
PQ0 E3 T6CCP0 SSI3Clk EPI0S20
PQ1 E2 T6CCP1 SSI3Fss EPI0S21
PQ2 H4 T7CCP0 SSI3XDAT0 EPI0S22
PQ3 M4 T7CCP1 SSI3XDAT1 EPI0S23
PQ4 A13 U1Rx DIVSCLK
PQ5 W12 U1Tx EN0RXD0
PQ6 U15 U1DTR EN0RXD1
PQ7 M3 U1RI
PR0 N5 U4Tx I2C1SCL M0PWM0 LCDCP
PR1 N4 U4Rx I2C1SDA M0PWM1 LCDFP
PR2 N2 I2C2SCL M0PWM2 LCDLP
PR3 V8 I2C2SDA M0PWM3 LCDDATA03
PR4 P3 I2C3SCL T0CCP0 M0PWM4 LCDDATA00
PR5 P2 U1Rx I2C3SDA T0CCP1 M0PWM5 LCDDATA01
PR6 W9 U1Tx I2C4SCL T1CCP0 M0PWM6 LCDDATA04
PR7 R10 I2C4SDA T1CCP1 M0PWM7 EN0TXEN LCDDATA05
PS0 D12 T2CCP0 M0FAULT0 LCDDATA20
PS1 D13 T2CCP1 M0FAULT1 LCDDATA21
PS2 B14 U1DSR T3CCP0 M0FAULT2 LCDDATA22
PS3 A14 T3CCP1 M0FAULT3 LCDDATA23
PS4 V9 T4CCP0 PhA0 EN0TXD0 LCDDATA06
PS5 T13 T4CCP1 PhB0 EN0TXD1 LCDDATA07
PS6 U10 T5CCP0 IDX0 EN0RXER LCDDATA08
PS7 R13 T5CCP1 EN0RXDV LCDDATA09
PT0 W10 T6CCP0 CAN0Rx EN0RXD0 LCDDATA10
PT1 V10 T6CCP1 CAN0Tx EN0RXD1 LCDDATA11
PT2 E18 T7CCP0 CAN1Rx LCDDATA18
PT3 F17 T7CCP1 CAN1Tx LCDDATA19
The TMPRn signals are digital signals enabled and configured by the Hibernation module. All other signals listed in this column are analog signals.