MSP432P401M datasheet

SLAS826H March 2015 – June 2019 MSP432P401M , MSP432P401R

PRODUCTION DATA.

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

PZ|100
ZXH|80
RGC|64

Thermal pad, mechanical data (Package|Pins)

Orderable Information

slas826h_oa

Table 5-25 Digital Outputs, High-Drive I/Os

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	MAX	UNIT
V_OH	High-level output voltage (see Figure 5-25 and Figure 5-26)	I_(OHmax) = –5 mA⁽¹⁾	2.2 V	V_CC – 0.25	V_CC	V
		I_(OHmax) = –15 mA⁽²⁾	2.2 V	V_CC – 0.60	V_CC
		I_(OHmax) = –10 mA⁽¹⁾	3.0 V	V_CC – 0.25	V_CC
		I_(OHmax) = –20 mA⁽²⁾	3.0 V	V_CC – 0.50	V_CC
V_OL	Low-level output voltage (see Figure 5-23 and Figure 5-24)	I_(OLmax) = 5 mA⁽¹⁾	2.2 V	V_SS	V_SS + 0.25	V
		I_(OLmax) = 15 mA⁽²⁾	2.2 V	V_SS	V_SS + 0.60
		I_(OLmax) = 10 mA⁽¹⁾	3.0 V	V_SS	V_SS + 0.25
		I_(OLmax) = 20 mA⁽²⁾	3.0 V	V_SS	V_SS + 0.50
f_Px.y	Port output frequency (with RC load)⁽⁵⁾	V_CORE = 1.4 V, C_L = 80 pF, R_L⁽³⁾⁽⁴⁾	1.62 V	24		MHz
			2.2 V	24
			3.0 V	24
d_Px.y	Port output duty cycle (with RC load)	V_CORE = 1.4 V, C_L = 80 pF, R_L⁽³⁾⁽⁴⁾	1.62 V	45%	55%
			2.2 V	45%	55%
			3.0 V	45%	55%
f_{Port_CLK}	Clock output frequency⁽⁵⁾	V_CORE = 1.4 V, C_L = 80 pF⁽⁴⁾	1.62 V	24		MHz
			2.2 V	24
			3.0 V	24
d_{Port_CLK}	Clock output duty cycle	V_CORE = 1.4 V, C_L = 80 pF⁽⁴⁾	1.62 V	45%	55%
			2.2 V	45%	55%
			3.0 V	45%	55%
t_rise	Port output rise time	C_L = 80 pF⁽⁶⁾	1.62 V		8	ns
			2.2 V		5
			3.0 V		3
t_fall	Port output fall time	C_L = 80 pF⁽⁷⁾	1.62 V		8	ns
			2.2 V		5
			3.0 V		3

(1) The maximum total current, I_(OHmax) and I_(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop specified.

(2) The maximum total current, I_(OHmax) and I_(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage drop specified.

(3) A resistive divider with 2 × R1 and R1 = 3.2 kΩ between V_CC and V_SS is used as load. The output is connected to the center tap of the divider. C_L = 80 pF is connected to the output to V_SS.

(4) The output voltage reaches at least 20% and 80% V_CC at the specified toggle frequency.

(5) The port can output frequencies at least up to the specified limit, and it might support higher frequencies.

(6) Measured between 20% of V_CC to 80% of V_CC.

(7) Measured between 80% of V_CC to 20% of V_CC.

Table 5-26 lists the frequencies of the pin-oscillator ports. See Figure 5-27 and Figure 5-28 for the typical characteristics graphs.