Refer to the PDF data sheet for device specific package drawings
Each channel of the eight available channels has a control register that can select any of the device-level DMA sources as the final source for that corresponding channel. Table 6-36 lists the sources available for mapping to each channel, based on the value of the Source Configuration (SRCCFG) register. The DMA transfers are initiated upon rising edge of the selected DMA source.
|SRCCFG = 0||SRCCFG = 1||SRCCFG = 2||SRCCFG = 3||SRCCFG = 4||SRCCFG = 5||SRCCFG = 6||SRCCFG = 7|
|Channel 0||Reserved||eUSCI_A0 TX||eUSCI_B0 TX0||eUSCI_B3 TX1||eUSCI_B2 TX2||eUSCI_B1 TX3||TA0CCR0||AES256_Trigger0|
|Channel 1||Reserved||eUSCI_A0 RX||eUSCI_B0 RX0||eUSCI_B3 RX1||eUSCI_B2 RX2||eUSCI_B1 RX3||TA0CCR2||AES256_Trigger1|
|Channel 2||Reserved||eUSCI_A1 TX||eUSCI_B1 TX0||eUSCI_B0 TX1||eUSCI_B3 TX2||eUSCI_B2 TX3||TA1CCR0||AES256_Trigger2|
|Channel 3||Reserved||eUSCI_A1 RX||eUSCI_B1 RX0||eUSCI_B0 RX1||eUSCI_B3 RX2||eUSCI_B2 RX3||TA1CCR2||Reserved|
|Channel 4||Reserved||eUSCI_A2 TX||eUSCI_B2 TX0||eUSCI_B1 TX1||eUSCI_B0 TX2||eUSCI_B3 TX3||TA2CCR0||Reserved|
|Channel 5||Reserved||eUSCI_A2 RX||eUSCI_B2 RX0||eUSCI_B1 RX1||eUSCI_B0 RX2||eUSCI_B3 RX3||TA2CCR2||Reserved|
|Channel 6||Reserved||eUSCI_A3 TX||eUSCI_B3 TX0||eUSCI_B2 TX1||eUSCI_B1 TX2||eUSCI_B0 TX3||TA3CCR0||DMAE0
|Channel 7||Reserved||eUSCI_A3 RX||eUSCI_B3 RX0||eUSCI_B2 RX1||eUSCI_B1 RX2||eUSCI_B0 RX3||TA3CCR2||Precision ADC|
Any source marked as Reserved is unused. It may be used for software-controlled DMA tasks, but typically it is reserved for enhancement purposes on future devices.