MSP432P401M datasheet

SLAS826H March 2015 – June 2019 MSP432P401M , MSP432P401R

PRODUCTION DATA.

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

PZ|100
ZXH|80
RGC|64

Thermal pad, mechanical data (Package|Pins)

Orderable Information

slas826h_oa

Table 5-11 High-Frequency Crystal Oscillator, HFXT

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
I_DVCC,HFXT	HFXT oscillator crystal current HF mode at typical ESR	f_OSC = 1 MHz, HFXTBYPASS = 0, HFXTDRIVE = 0, HFFREQ = 0, C_L,eff = 16 pF, Typical ESR and C_SHUNT	3.0 V		40		µA
		f_OSC = 4 MHz, HFXTBYPASS = 0, HFXTDRIVE = 1, HFFREQ = 0, C_L,eff = 16 pF, Typical ESR and C_SHUNT			60
		f_OSC = 8 MHz, HFXTBYPASS = 0, HFXTDRIVE = 1, HFFREQ = 1, C_L,eff = 16 pF, Typical ESR and C_SHUNT			100
		f_OSC = 16 MHz, HFXTBYPASS = 0, HFXTDRIVE = 1, HFFREQ = 2, C_L,eff = 16 pF, Typical ESR and C_SHUNT			180
		f_OSC = 24 MHz, HFXTBYPASS = 0, HFXTDRIVE = 1, HFFREQ = 3, C_L,eff = 16 pF, Typical ESR and C_SHUNT			260
		f_OSC = 32 MHz, HFXTBYPASS = 0, HFXTDRIVE = 1, HFFREQ = 4, C_L,eff = 16 pF, Typical ESR and C_SHUNT			320
		f_OSC = 40 MHz, HFXTBYPASS = 0, HFXTDRIVE = 1, HFFREQ = 5, C_L,eff = 16 pF, Typical ESR and C_SHUNT			480
		f_OSC = 48 MHz, HFXTBYPASS = 0, HFXTDRIVE = 1, HFFREQ = 6, C_L,eff = 16 pF, Typical ESR and C_SHUNT			550
f_HFXT	HFXT oscillator crystal frequency, crystal mode	HFXTBYPASS = 0, HFFREQ = 0 ⁽⁶⁾		1		4	MHz
		HFXTBYPASS = 0, HFFREQ = 1 ⁽⁶⁾		4.01		8
		HFXTBYPASS = 0, HFFREQ = 2 ⁽⁶⁾		8.01		16
		HFXTBYPASS = 0, HFFREQ = 3 ⁽⁶⁾		16.01		24
		HFXTBYPASS = 0, HFFREQ = 4 ⁽⁶⁾		24.01		32
		HFXTBYPASS = 0, HFFREQ = 5 ⁽⁶⁾		32.01		40
		HFXTBYPASS = 0, HFFREQ = 6 ⁽⁶⁾		40.01		48
DC_HFXT	HFXT oscillator duty cycle	Measured at MCLK or HSMCLK, f_HFXT = 1 MHz to 48 MHz		40%	50%	60%
f_HFXT,SW	HFXT oscillator logic-level square-wave input frequency, bypass mode	HFXTBYPASS = 1⁽⁶⁾⁽⁵⁾		0.8		48	MHz
DC_{HFXT, SW}	HFXT oscillator logic-level square-wave input duty cycle	HFXTBYPASS = 1, External clock used as a direct source to MCLK or HSMCLK with no divider (DIVM = 0 or DIVHS = 0).		45%		55%
DC_{HFXT, SW}	HFXT oscillator logic-level square-wave input duty cycle	HFXTBYPASS = 1, External clock used as a direct source to MCLK or HSMCLK with divider (DIVM > 0 or DIVHS > 0) or not used as a direct source to MCLK or HSMCLK.		40%		60%
OA_HFXT	Oscillation allowance for HFXT crystals⁽⁷⁾	HFXTBYPASS = 0, HFXTDRIVE = 0, HFFREQ = 0, f_HFXT,HF = 1 MHz, C_L,eff = 16 pF		1225	5000		Ω
		HFXTBYPASS = 0, HFXTDRIVE = 1, HFFREQ = 0, f_HFXT,HF = 4 MHz, C_L,eff = 16 pF		640	1250
		HFXTBYPASS = 0, HFXTDRIVE = 1, HFFREQ = 1, f_HFXT,HF = 8 MHz, C_L,eff = 16 pF		360	750
		HFXTBYPASS = 0, HFXTDRIVE = 1, HFFREQ = 2, f_HFXT,HF = 16 MHz, C_L,eff = 16 pF		200	425
		HFXTBYPASS = 0, HFXTDRIVE = 1, HFFREQ = 3, f_HFXT,HF = 24 MHz, C_L,eff = 16 pF		135	275
		HFXTBYPASS = 0, HFXTDRIVE = 1, HFFREQ = 4, f_HFXT,HF = 32 MHz, C_L,eff = 16 pF		110	225
		HFXTBYPASS = 0, HFXTDRIVE = 1, HFFREQ = 5 f_HFXT,HF = 40 MHz, C_L,eff = 16 pF		105	160
		HFXTBYPASS = 0, HFXTDRIVE = 1, HFFREQ = 6, f_HFXT,HF = 48 MHz, C_L,eff = 16 pF		80	140
t_START,HFXT	Start-up time⁽⁸⁾	f_OSC = 1 MHz, HFXTBYPASS = 0, HFXTDRIVE = 0, HFFREQ = 0, C_L,eff = 16 pF, Typical ESR and C_SHUNT, FCNTHF_EN = 0	3.0 V		4		ms
		f_OSC = 4 MHz, HFXTBYPASS = 0, HFXTDRIVE = 1, HFFREQ = 0, C_L,eff = 16 pF, Typical ESR and C_SHUNT, FCNTHF_EN = 0			1.8
		f_OSC = 8 MHz, HFXTBYPASS = 0, HFXTDRIVE = 1, HFFREQ = 1, C_L,eff = 16 pF, Typical ESR and C_SHUNT, FCNTHF_EN = 0			0.7
		f_OSC = 16 MHz, HFXTBYPASS = 0, HFXTDRIVE = 1, HFFREQ = 2, C_L,eff = 16 pF, Typical ESR and C_SHUNT, FCNTHF_EN = 0			0.6
		f_OSC = 24 MHz, HFXTBYPASS = 0, HFXTDRIVE = 1, HFFREQ = 3, C_L,eff = 16 pF, Typical ESR and C_SHUNT, FCNTHF_EN = 0			450		µs
		f_OSC = 32 MHz, HFXTBYPASS = 0, HFXTDRIVE = 1, HFFREQ = 4, C_L,eff = 16 pF, Typical ESR and C_SHUNT, FCNTHF_EN = 0			300
		f_OSC = 40 MHz, HFXTBYPASS = 0, HFXTDRIVE = 1, HFFREQ = 5, C_L,eff = 16 pF, Typical ESR and C_SHUNT, FCNTHF_EN = 0			250
		f_OSC = 48 MHz, HFXTBYPASS = 0, HFXTDRIVE = 1, HFFREQ = 6, C_L,eff = 16 pF, Typical ESR and C_SHUNT, FCNTHF_EN = 0			250
C_HFXIN	Integrated load capacitance at HFXIN terminal⁽¹⁾⁽²⁾				2		pF
C_HFXOUT	Integrated load capacitance at HFXOUT terminal⁽¹⁾⁽²⁾				2		pF
f_Fault,HFXT	Oscillator fault frequency⁽⁴⁾⁽³⁾			400		700	kHz

(1) This represents all the parasitic capacitance present at the HFXIN and HFXOUT terminals, respectively, including parasitic bond and package capacitance. The effective load capacitance, CL,eff can be computed as CIN x COUT / (CIN + COUT), where CIN and COUT is the total capacitance at the HFXIN and HFXOUT terminals, respectively.

(2) Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers. Recommended effective load capacitance values supported are 14 pF, 16 pF, and 18 pF. Maximum shunt capacitance of 7 pF. Because the PCB adds additional capacitance, it must also be considered in the overall capacitance. TI recommends verifying that the recommended effective load capacitance of the selected crystal is met.

(3) Measured with logic-level input frequency but also applies to operation with crystals.

(4) Frequencies above the MAX specification do not set the fault flag. Frequencies in between the MIN and MAX might set the flag. A static condition or stuck at fault condition will set the flag.

(5) When HFXTBYPASS is set, HFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in the Schmitt-trigger Inputs section of this data sheet. Duty cycle requirements are defined by DC_{HFXT, SW}.

(6) Maximum frequency of operation of the entire device cannot be exceeded.

(7) Oscillation allowance is based on a safety factor of 5 for recommended crystals.

(8) Does not include programable start-up counter.

Table 5-12 lists the characteristics of the DCO.