Refer to the PDF data sheet for device specific package drawings
The Cortex-M4 processor on MSP432P401x MCUs implements an NVIC with 64 external interrupt lines and 8 levels of priority. From an application perspective, the interrupt sources at the device level are divided into two classes, the NMI and the User Interrupts. Internally, the CPU exception model handles the various exceptions (internal and external events including CPU instruction, memory, and bus fault conditions) in a fixed and configurable order of priority. For details on the handling of various exception priorities (including CPU reset and fault models), see the Arm-V7M architecture reference manual at www.arm.com.