SLAS826H March 2015 – June 2019 MSP432P401M , MSP432P401R
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
The NVIC supports up to 64 interrupts with eight levels of interrupt priority. The Cortex-M4 NVIC architecture allows for low latency, efficient interrupt and event handling, and seamless integration to device-level power-control strategies.