SLAS826H March   2015  – June 2019 MSP432P401M , MSP432P401R

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. Table 4-2 Signal Descriptions
    4. 4.4 Pin Multiplexing
    5. 4.5 Buffer Types
    6. 4.6 Connection for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Recommended External Components
    5. 5.5  Operating Mode VCC Ranges
    6. 5.6  Operating Mode CPU Frequency Ranges
    7. 5.7  Operating Mode Peripheral Frequency Ranges
    8. 5.8  Operating Mode Execution Frequency vs Flash Wait-State Requirements
    9. 5.9  Current Consumption During Device Reset of the 100-pin LQFP Package
    10. 5.10 Current Consumption in LDO-Based Active Modes – Dhrystone 2.1 Program
    11. 5.11 Current Consumption in DC-DC-Based Active Modes – Dhrystone 2.1 Program
    12. 5.12 Current Consumption in Low-Frequency Active Modes – Dhrystone 2.1 Program
    13. 5.13 Typical Characteristics of Active Mode Currents for CoreMark Program
    14. 5.14 Typical Characteristics of Active Mode Currents for Prime Number Program
    15. 5.15 Typical Characteristics of Active Mode Currents for Fibonacci Program
    16. 5.16 Typical Characteristics of Active Mode Currents for While(1) Program
    17. 5.17 Typical Characteristics of Low-Frequency Active Mode Currents for CoreMark Program
    18. 5.18 Current Consumption in LDO-Based LPM0 Modes
    19. 5.19 Current Consumption in DC-DC-Based LPM0 Modes
    20. 5.20 Current Consumption in Low-Frequency LPM0 Modes
    21. 5.21 Current Consumption in LPM3, LPM4 Modes
    22. 5.22 Current Consumption in LPM3.5, LPM4.5 Modes
    23. 5.23 Current Consumption of Digital Peripherals
    24. 5.24 Thermal Resistance Characteristics
    25. 5.25 Timing and Switching Characteristics
      1. 5.25.1  Reset Timing
        1. Table 5-1 Reset Recovery Latencies
        2. Table 5-2 External Reset Recovery Latencies
      2. 5.25.2  Peripheral Register Access Timing
        1. Table 5-3 Peripheral Register Access Latency
      3. 5.25.3  Mode Transition Timing
        1. Table 5-4 Active Mode Transition Latencies
        2. Table 5-5 LPM0 Mode Transition Latencies
        3. Table 5-6 LPM3, LPM4 Mode Transition Latencies
        4. Table 5-7 LPM3.5, LPM4.5 Mode Transition Latencies
      4. 5.25.4  Clock Specifications
        1. Table 5-8  Low-Frequency Crystal Oscillator, LFXT, Recommended Operating Conditions
        2. Table 5-9  Low-Frequency Crystal Oscillator, LFXT
        3. Table 5-10 High-Frequency Crystal Oscillator, HFXT, Recommended Operating Conditions
        4. Table 5-11 High-Frequency Crystal Oscillator, HFXT
        5. Table 5-12 DCO
        6. Table 5-13 DCO Overall Tolerance
        7. Table 5-14 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        8. Table 5-15 Internal-Reference Low-Frequency Oscillator (REFO) in 32.768-kHz Mode
        9. Table 5-16 Internal-Reference Low-Frequency Oscillator (REFO) in 128-kHz Mode
        10. Table 5-17 Module Oscillator (MODOSC)
        11. Table 5-18 System Oscillator (SYSOSC)
      5. 5.25.5  Power Supply System
        1. Table 5-19 VCORE Regulator (LDO) Characteristics
        2. Table 5-20 VCORE Regulator (DC-DC) Characteristics
        3. Table 5-21 PSS, VCCDET
        4. Table 5-22 PSS, SVSMH
      6. 5.25.6  Digital I/Os
        1. Table 5-23 Digital Inputs (Applies to Both Normal and High-Drive I/Os)
        2. Table 5-24 Digital Outputs, Normal I/Os
        3. Table 5-25 Digital Outputs, High-Drive I/Os
        4. Table 5-26 Pin-Oscillator Frequency, Ports Px
        5. 5.25.6.1   Typical Characteristics, Normal-Drive I/O Outputs at 3.0 V and 2.2 V
        6. 5.25.6.2   Typical Characteristics, High-Drive I/O Outputs at 3.0 V and 2.2 V
        7. 5.25.6.3   Typical Characteristics, Pin-Oscillator Frequency
      7. 5.25.7  Precision ADC
        1. Table 5-27 Precision ADC, Power Supply and Input Range Conditions
        2. Table 5-28 Precision ADC, Timing Parameters
        3. Table 5-29 Precision ADC, Linearity Parameters
        4. Table 5-30 Precision ADC, Dynamic Parameters
        5. Table 5-31 Precision ADC, Temperature Sensor and Built-In V1/2
        6. Table 5-32 Precision ADC, Internal Reference Buffers
        7. Table 5-33 Precision ADC, External Reference
        8. 5.25.7.1   Typical Characteristics of ADC
      8. 5.25.8  REF_A
        1. Table 5-34 REF_A, Built-In Reference (LDO Operation)
      9. 5.25.9  Comparator_E
        1. Table 5-35 Comparator_E
      10. 5.25.10 eUSCI
        1. Table 5-36 eUSCI Clock Frequency (UART Mode)
        2. Table 5-37 eUSCI Switching Characteristics (UART Mode)
        3. Table 5-38 eUSCI Clock Frequency (SPI Master Mode)
        4. Table 5-39 eUSCI Switching Characteristics (SPI Master Mode)
        5. Table 5-40 eUSCI Switching Characteristics (SPI Slave Mode)
        6. Table 5-41 eUSCI Clock Frequency (I2C Mode)
        7. Table 5-42 eUSCI Switching Characteristics (I2C Mode)
      11. 5.25.11 Timers
        1. Table 5-43 Timer_A
        2. Table 5-44 Timer32
      12. 5.25.12 Memories
        1. Table 5-45 Flash Memory
        2. Table 5-46 Flash Operations Using MSP432 Peripheral Driver Libraries
        3. Table 5-47 Flash Stand-Alone Operations
        4. Table 5-48 SRAM
      13. 5.25.13 Emulation and Debug
        1. Table 5-49 JTAG
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  Processor and Execution Features
      1. 6.2.1 Floating-Point Unit
      2. 6.2.2 Memory Protection Unit
      3. 6.2.3 Nested Vectored Interrupt Controller (NVIC)
      4. 6.2.4 SysTick
      5. 6.2.5 Debug and Trace Features
    3. 6.3  Memory Map
      1. 6.3.1 Code Zone Memory Map
        1. 6.3.1.1 Flash Memory Region
        2. 6.3.1.2 SRAM Region
        3. 6.3.1.3 ROM Region
      2. 6.3.2 SRAM Zone Memory Map
        1. 6.3.2.1 SRAM Region
        2. 6.3.2.2 SRAM Bit-Band Alias Region
      3. 6.3.3 Peripheral Zone Memory Map
        1. 6.3.3.1 Peripheral Region
        2. 6.3.3.2 Peripheral Bit Band Alias Region
      4. 6.3.4 Debug and Trace Peripheral Zone
    4. 6.4  Memories on the MSP432P401x
      1. 6.4.1 Flash Memory
        1. 6.4.1.1 Flash Main Memory (0x0000_0000 to 0x0003_FFFF)
        2. 6.4.1.2 Flash Information Memory (0x0020_0000 to 0x0020_3FFF)
        3. 6.4.1.3 Flash Operation
      2. 6.4.2 SRAM
        1. 6.4.2.1 SRAM Bank Enable Configuration
        2. 6.4.2.2 SRAM Bank Retention Configuration and Backup Memory
      3. 6.4.3 ROM
    5. 6.5  DMA
      1. 6.5.1 DMA Source Mapping
      2. 6.5.2 DMA Completion Interrupts
      3. 6.5.3 DMA Access Privileges
    6. 6.6  Memory Map Access Details
      1. 6.6.1 Master and Slave Access Priority Settings
      2. 6.6.2 Memory Map Access Response
    7. 6.7  Interrupts
      1. 6.7.1 NMI
      2. 6.7.2 Device-Level User Interrupts
    8. 6.8  System Control
      1. 6.8.1 Device Resets
        1. 6.8.1.1 Power On/Off Reset (POR)
        2. 6.8.1.2 Reboot Reset
        3. 6.8.1.3 Hard Reset
        4. 6.8.1.4 Soft Reset
      2. 6.8.2 Power Supply System (PSS)
        1. 6.8.2.1 VCCDET
        2. 6.8.2.2 Supply Supervisor and Monitor for High Side (SVSMH)
        3. 6.8.2.3 Core Voltage Regulator
      3. 6.8.3 Power Control Manager (PCM)
      4. 6.8.4 Clock System (CS)
        1. 6.8.4.1 LFXT
        2. 6.8.4.2 HFXT
        3. 6.8.4.3 DCO
        4. 6.8.4.4 Very Low-Power Low-Frequency Oscillator (VLO)
        5. 6.8.4.5 Low-Frequency Reference Oscillator (REFO)
        6. 6.8.4.6 Module Oscillator (MODOSC)
        7. 6.8.4.7 System Oscillator (SYSOSC)
        8. 6.8.4.8 Fail-Safe Mechanisms
      5. 6.8.5 System Controller (SYSCTL)
    9. 6.9  Peripherals
      1. 6.9.1  Digital I/O
        1. 6.9.1.1 Glitch Filtering on Digital I/Os
      2. 6.9.2  Port Mapping Controller (PMAPCTL)
        1. 6.9.2.1 Port Mapping Definitions
      3. 6.9.3  Timer_A
        1. 6.9.3.1 Timer_A Signal Connection Tables
      4. 6.9.4  Timer32
      5. 6.9.5  Enhanced Universal Serial Communication Interface (eUSCI)
      6. 6.9.6  Real-Time Clock (RTC_C)
      7. 6.9.7  Watchdog Timer (WDT_A)
      8. 6.9.8  Precision ADC
      9. 6.9.9  Comparator_E (COMP_E)
      10. 6.9.10 Shared Reference (REF_A)
      11. 6.9.11 CRC32
      12. 6.9.12 AES256 Accelerator
      13. 6.9.13 True Random Seed
    10. 6.10 Code Development and Debug
      1. 6.10.1 JTAG and SWD Based Development, Debug, and Trace
      2. 6.10.2 Peripheral Halt Control
      3. 6.10.3 Bootloader (BSL)
      4. 6.10.4 Device Security
    11. 6.11 Performance Benchmarks
      1. 6.11.1 ULPBench Performance: 192.3 ULPMark-CP
      2. 6.11.2 CoreMark/MHz Performance: 3.41
      3. 6.11.3 DMIPS/MHz (Dhrystone 2.1) Performance: 1.22
    12. 6.12 Input/Output Diagrams
      1. 6.12.1  Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 6.12.2  Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger
      3. 6.12.3  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      4. 6.12.4  Port P9 (P9.4 to P9.7) Input/Output With Schmitt Trigger
      5. 6.12.5  Port P10 (P10.0 to P10.3) Input/Output With Schmitt Trigger
      6. 6.12.6  Port P2 (P2.4 to P2.7) Input/Output With Schmitt Trigger
      7. 6.12.7  Port P7 (P7.0 to P7.3) Input/Output With Schmitt Trigger
      8. 6.12.8  Port P9 (P9.2 and P9.3) Input/Output With Schmitt Trigger
      9. 6.12.9  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      10. 6.12.10 Port P5 (P5.0 to P5.5) Input/Output With Schmitt Trigger
      11. 6.12.11 Port P6 (P6.0 and P6.1) Input/Output With Schmitt Trigger
      12. 6.12.12 Port P8 (P8.2 to P8.7) Input/Output With Schmitt Trigger
      13. 6.12.13 Port P9 (P9.0 and P9.1) Input/Output With Schmitt Trigger
      14. 6.12.14 Port P5 (P5.6 and P5.7) Input/Output With Schmitt Trigger
      15. 6.12.15 Port P6 (P6.2 to P6.5) Input/Output With Schmitt Trigger
      16. 6.12.16 Port P6 (P6.6 and P6.7) Input/Output With Schmitt Trigger
      17. 6.12.17 Port P8 (P8.0 and P8.1) Input/Output With Schmitt Trigger
      18. 6.12.18 Port P10 (P10.4 and P10.5) Input/Output With Schmitt Trigger
      19. 6.12.19 Port P7 (P7.4 to P7.7) Input/Output With Schmitt Trigger
      20. 6.12.20 Port PJ (PJ.0 and PJ.1) Input/Output With Schmitt Trigger
      21. 6.12.21 Port PJ (PJ.2 and PJ.3) Input/Output With Schmitt Trigger
      22. 6.12.22 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
      23. 6.12.23 Ports SWCLKTCK and SWDIOTMS With Schmitt Trigger
    13. 6.13 Device Descriptors (TLV)
    14. 6.14 Identification
      1. 6.14.1 Revision Identification
      2. 6.14.2 Device Identification
      3. 6.14.3 Arm Cortex-M4F ROM Table Based Part Number
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 General Layout Recommendations
      4. 7.1.4 Do's and Don'ts
    2. 7.2 Peripheral and Interface-Specific Design Information
      1. 7.2.1 Precision ADC Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Layout Guidelines
  8. 8Device and Documentation Support
    1. 8.1  Getting Started and Next Steps
    2. 8.2  Device Nomenclature
    3. 8.3  Tools and Software
    4. 8.4  Documentation Support
    5. 8.5  Related Links
    6. 8.6  Community Resources
    7. 8.7  Trademarks
    8. 8.8  Electrostatic Discharge Caution
    9. 8.9  Export Control Notice
    10. 8.10 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PZ|100
  • ZXH|80
  • RGC|64
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.2.3 Nested Vectored Interrupt Controller (NVIC)

The NVIC supports up to 64 interrupts with eight levels of interrupt priority. The Cortex-M4 NVIC architecture allows for low latency, efficient interrupt and event handling, and seamless integration to device-level power-control strategies.