SLAS826H March   2015  – June 2019 MSP432P401M , MSP432P401R


  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. Table 4-2 Signal Descriptions
    4. 4.4 Pin Multiplexing
    5. 4.5 Buffer Types
    6. 4.6 Connection for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Recommended External Components
    5. 5.5  Operating Mode VCC Ranges
    6. 5.6  Operating Mode CPU Frequency Ranges
    7. 5.7  Operating Mode Peripheral Frequency Ranges
    8. 5.8  Operating Mode Execution Frequency vs Flash Wait-State Requirements
    9. 5.9  Current Consumption During Device Reset of the 100-pin LQFP Package
    10. 5.10 Current Consumption in LDO-Based Active Modes – Dhrystone 2.1 Program
    11. 5.11 Current Consumption in DC-DC-Based Active Modes – Dhrystone 2.1 Program
    12. 5.12 Current Consumption in Low-Frequency Active Modes – Dhrystone 2.1 Program
    13. 5.13 Typical Characteristics of Active Mode Currents for CoreMark Program
    14. 5.14 Typical Characteristics of Active Mode Currents for Prime Number Program
    15. 5.15 Typical Characteristics of Active Mode Currents for Fibonacci Program
    16. 5.16 Typical Characteristics of Active Mode Currents for While(1) Program
    17. 5.17 Typical Characteristics of Low-Frequency Active Mode Currents for CoreMark Program
    18. 5.18 Current Consumption in LDO-Based LPM0 Modes
    19. 5.19 Current Consumption in DC-DC-Based LPM0 Modes
    20. 5.20 Current Consumption in Low-Frequency LPM0 Modes
    21. 5.21 Current Consumption in LPM3, LPM4 Modes
    22. 5.22 Current Consumption in LPM3.5, LPM4.5 Modes
    23. 5.23 Current Consumption of Digital Peripherals
    24. 5.24 Thermal Resistance Characteristics
    25. 5.25 Timing and Switching Characteristics
      1. 5.25.1  Reset Timing
        1. Table 5-1 Reset Recovery Latencies
        2. Table 5-2 External Reset Recovery Latencies
      2. 5.25.2  Peripheral Register Access Timing
        1. Table 5-3 Peripheral Register Access Latency
      3. 5.25.3  Mode Transition Timing
        1. Table 5-4 Active Mode Transition Latencies
        2. Table 5-5 LPM0 Mode Transition Latencies
        3. Table 5-6 LPM3, LPM4 Mode Transition Latencies
        4. Table 5-7 LPM3.5, LPM4.5 Mode Transition Latencies
      4. 5.25.4  Clock Specifications
        1. Table 5-8  Low-Frequency Crystal Oscillator, LFXT, Recommended Operating Conditions
        2. Table 5-9  Low-Frequency Crystal Oscillator, LFXT
        3. Table 5-10 High-Frequency Crystal Oscillator, HFXT, Recommended Operating Conditions
        4. Table 5-11 High-Frequency Crystal Oscillator, HFXT
        5. Table 5-12 DCO
        6. Table 5-13 DCO Overall Tolerance
        7. Table 5-14 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        8. Table 5-15 Internal-Reference Low-Frequency Oscillator (REFO) in 32.768-kHz Mode
        9. Table 5-16 Internal-Reference Low-Frequency Oscillator (REFO) in 128-kHz Mode
        10. Table 5-17 Module Oscillator (MODOSC)
        11. Table 5-18 System Oscillator (SYSOSC)
      5. 5.25.5  Power Supply System
        1. Table 5-19 VCORE Regulator (LDO) Characteristics
        2. Table 5-20 VCORE Regulator (DC-DC) Characteristics
        3. Table 5-21 PSS, VCCDET
        4. Table 5-22 PSS, SVSMH
      6. 5.25.6  Digital I/Os
        1. Table 5-23 Digital Inputs (Applies to Both Normal and High-Drive I/Os)
        2. Table 5-24 Digital Outputs, Normal I/Os
        3. Table 5-25 Digital Outputs, High-Drive I/Os
        4. Table 5-26 Pin-Oscillator Frequency, Ports Px
        5.   Typical Characteristics, Normal-Drive I/O Outputs at 3.0 V and 2.2 V
        6.   Typical Characteristics, High-Drive I/O Outputs at 3.0 V and 2.2 V
        7.   Typical Characteristics, Pin-Oscillator Frequency
      7. 5.25.7  Precision ADC
        1. Table 5-27 Precision ADC, Power Supply and Input Range Conditions
        2. Table 5-28 Precision ADC, Timing Parameters
        3. Table 5-29 Precision ADC, Linearity Parameters
        4. Table 5-30 Precision ADC, Dynamic Parameters
        5. Table 5-31 Precision ADC, Temperature Sensor and Built-In V1/2
        6. Table 5-32 Precision ADC, Internal Reference Buffers
        7. Table 5-33 Precision ADC, External Reference
        8.   Typical Characteristics of ADC
      8. 5.25.8  REF_A
        1. Table 5-34 REF_A, Built-In Reference (LDO Operation)
      9. 5.25.9  Comparator_E
        1. Table 5-35 Comparator_E
      10. 5.25.10 eUSCI
        1. Table 5-36 eUSCI Clock Frequency (UART Mode)
        2. Table 5-37 eUSCI Switching Characteristics (UART Mode)
        3. Table 5-38 eUSCI Clock Frequency (SPI Master Mode)
        4. Table 5-39 eUSCI Switching Characteristics (SPI Master Mode)
        5. Table 5-40 eUSCI Switching Characteristics (SPI Slave Mode)
        6. Table 5-41 eUSCI Clock Frequency (I2C Mode)
        7. Table 5-42 eUSCI Switching Characteristics (I2C Mode)
      11. 5.25.11 Timers
        1. Table 5-43 Timer_A
        2. Table 5-44 Timer32
      12. 5.25.12 Memories
        1. Table 5-45 Flash Memory
        2. Table 5-46 Flash Operations Using MSP432 Peripheral Driver Libraries
        3. Table 5-47 Flash Stand-Alone Operations
        4. Table 5-48 SRAM
      13. 5.25.13 Emulation and Debug
        1. Table 5-49 JTAG
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  Processor and Execution Features
      1. 6.2.1 Floating-Point Unit
      2. 6.2.2 Memory Protection Unit
      3. 6.2.3 Nested Vectored Interrupt Controller (NVIC)
      4. 6.2.4 SysTick
      5. 6.2.5 Debug and Trace Features
    3. 6.3  Memory Map
      1. 6.3.1 Code Zone Memory Map
        1. Flash Memory Region
        2. SRAM Region
        3. ROM Region
      2. 6.3.2 SRAM Zone Memory Map
        1. SRAM Region
        2. SRAM Bit-Band Alias Region
      3. 6.3.3 Peripheral Zone Memory Map
        1. Peripheral Region
        2. Peripheral Bit Band Alias Region
      4. 6.3.4 Debug and Trace Peripheral Zone
    4. 6.4  Memories on the MSP432P401x
      1. 6.4.1 Flash Memory
        1. Flash Main Memory (0x0000_0000 to 0x0003_FFFF)
        2. Flash Information Memory (0x0020_0000 to 0x0020_3FFF)
        3. Flash Operation
      2. 6.4.2 SRAM
        1. SRAM Bank Enable Configuration
        2. SRAM Bank Retention Configuration and Backup Memory
      3. 6.4.3 ROM
    5. 6.5  DMA
      1. 6.5.1 DMA Source Mapping
      2. 6.5.2 DMA Completion Interrupts
      3. 6.5.3 DMA Access Privileges
    6. 6.6  Memory Map Access Details
      1. 6.6.1 Master and Slave Access Priority Settings
      2. 6.6.2 Memory Map Access Response
    7. 6.7  Interrupts
      1. 6.7.1 NMI
      2. 6.7.2 Device-Level User Interrupts
    8. 6.8  System Control
      1. 6.8.1 Device Resets
        1. Power On/Off Reset (POR)
        2. Reboot Reset
        3. Hard Reset
        4. Soft Reset
      2. 6.8.2 Power Supply System (PSS)
        1. VCCDET
        2. Supply Supervisor and Monitor for High Side (SVSMH)
        3. Core Voltage Regulator
      3. 6.8.3 Power Control Manager (PCM)
      4. 6.8.4 Clock System (CS)
        1. LFXT
        2. HFXT
        3. DCO
        4. Very Low-Power Low-Frequency Oscillator (VLO)
        5. Low-Frequency Reference Oscillator (REFO)
        6. Module Oscillator (MODOSC)
        7. System Oscillator (SYSOSC)
        8. Fail-Safe Mechanisms
      5. 6.8.5 System Controller (SYSCTL)
    9. 6.9  Peripherals
      1. 6.9.1  Digital I/O
        1. Glitch Filtering on Digital I/Os
      2. 6.9.2  Port Mapping Controller (PMAPCTL)
        1. Port Mapping Definitions
      3. 6.9.3  Timer_A
        1. Timer_A Signal Connection Tables
      4. 6.9.4  Timer32
      5. 6.9.5  Enhanced Universal Serial Communication Interface (eUSCI)
      6. 6.9.6  Real-Time Clock (RTC_C)
      7. 6.9.7  Watchdog Timer (WDT_A)
      8. 6.9.8  Precision ADC
      9. 6.9.9  Comparator_E (COMP_E)
      10. 6.9.10 Shared Reference (REF_A)
      11. 6.9.11 CRC32
      12. 6.9.12 AES256 Accelerator
      13. 6.9.13 True Random Seed
    10. 6.10 Code Development and Debug
      1. 6.10.1 JTAG and SWD Based Development, Debug, and Trace
      2. 6.10.2 Peripheral Halt Control
      3. 6.10.3 Bootloader (BSL)
      4. 6.10.4 Device Security
    11. 6.11 Performance Benchmarks
      1. 6.11.1 ULPBench Performance: 192.3 ULPMark-CP
      2. 6.11.2 CoreMark/MHz Performance: 3.41
      3. 6.11.3 DMIPS/MHz (Dhrystone 2.1) Performance: 1.22
    12. 6.12 Input/Output Diagrams
      1. 6.12.1  Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 6.12.2  Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger
      3. 6.12.3  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      4. 6.12.4  Port P9 (P9.4 to P9.7) Input/Output With Schmitt Trigger
      5. 6.12.5  Port P10 (P10.0 to P10.3) Input/Output With Schmitt Trigger
      6. 6.12.6  Port P2 (P2.4 to P2.7) Input/Output With Schmitt Trigger
      7. 6.12.7  Port P7 (P7.0 to P7.3) Input/Output With Schmitt Trigger
      8. 6.12.8  Port P9 (P9.2 and P9.3) Input/Output With Schmitt Trigger
      9. 6.12.9  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      10. 6.12.10 Port P5 (P5.0 to P5.5) Input/Output With Schmitt Trigger
      11. 6.12.11 Port P6 (P6.0 and P6.1) Input/Output With Schmitt Trigger
      12. 6.12.12 Port P8 (P8.2 to P8.7) Input/Output With Schmitt Trigger
      13. 6.12.13 Port P9 (P9.0 and P9.1) Input/Output With Schmitt Trigger
      14. 6.12.14 Port P5 (P5.6 and P5.7) Input/Output With Schmitt Trigger
      15. 6.12.15 Port P6 (P6.2 to P6.5) Input/Output With Schmitt Trigger
      16. 6.12.16 Port P6 (P6.6 and P6.7) Input/Output With Schmitt Trigger
      17. 6.12.17 Port P8 (P8.0 and P8.1) Input/Output With Schmitt Trigger
      18. 6.12.18 Port P10 (P10.4 and P10.5) Input/Output With Schmitt Trigger
      19. 6.12.19 Port P7 (P7.4 to P7.7) Input/Output With Schmitt Trigger
      20. 6.12.20 Port PJ (PJ.0 and PJ.1) Input/Output With Schmitt Trigger
      21. 6.12.21 Port PJ (PJ.2 and PJ.3) Input/Output With Schmitt Trigger
      22. 6.12.22 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
      23. 6.12.23 Ports SWCLKTCK and SWDIOTMS With Schmitt Trigger
    13. 6.13 Device Descriptors (TLV)
    14. 6.14 Identification
      1. 6.14.1 Revision Identification
      2. 6.14.2 Device Identification
      3. 6.14.3 Arm Cortex-M4F ROM Table Based Part Number
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 General Layout Recommendations
      4. 7.1.4 Do's and Don'ts
    2. 7.2 Peripheral and Interface-Specific Design Information
      1. 7.2.1 Precision ADC Peripheral
        1. Partial Schematic
        2. Design Requirements
        3. Layout Guidelines
  8. 8Device and Documentation Support
    1. 8.1  Getting Started and Next Steps
    2. 8.2  Device Nomenclature
    3. 8.3  Tools and Software
    4. 8.4  Documentation Support
    5. 8.5  Related Links
    6. 8.6  Community Resources
    7. 8.7  Trademarks
    8. 8.8  Electrostatic Discharge Caution
    9. 8.9  Export Control Notice
    10. 8.10 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PZ|100
  • ZXH|80
  • RGC|64
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Peripheral Region

The 1MB region from 0x4000_0000 to 0x400F_FFFF is dedicated to the system and application control peripherals of the device. On the MSP432P401x MCUs, a total of 128KB of this region is dedicated for peripherals, while the rest is reserved. Table 6-1 lists the peripheral allocation within this 128-KB space. Note that all peripherals may not be available in all devices of the family (details in the REMARKS column). If a peripheral is listed as N/A for a particular device, treat the corresponding address space as reserved.


Peripherals that are marked as 16-bit should be accessed through byte or half-word size read or write only. Any 32-bit access to these peripherals results in a bus error response.

Table 6-1 Peripheral Address Offsets

0x4000_0000 to 0x4000_03FF Timer_A0 Table 6-2 16-bit peripheral
0x4000_0400 to 0x4000_07FF Timer_A1 Table 6-3 16-bit peripheral
0x4000_0800 to 0x4000_0BFF Timer_A2 Table 6-4 16-bit peripheral
0x4000_0C00 to 0x4000_0FFF Timer_A3 Table 6-5 16-bit peripheral
0x4000_1000 to 0x4000_13FF eUSCI_A0 Table 6-6 16-bit peripheral
0x4000_1400 to 0x4000_17FF eUSCI_A1 Table 6-7 16-bit peripheral
0x4000_1800 to 0x4000_1BFF eUSCI_A2 Table 6-8 16-bit peripheral
0x4000_1C00 to 0x4000_1FFF eUSCI_A3 Table 6-9 16-bit peripheral
0x4000_2000 to 0x4000_23FF eUSCI_B0 Table 6-10 16-bit peripheral
0x4000_2400 to 0x4000_27FF eUSCI_B1 Table 6-11 16-bit peripheral
0x4000_2800 to 0x4000_2BFF eUSCI_B2 Table 6-12 16-bit peripheral
0x4000_2C00 to 0x4000_2FFF eUSCI_B3 Table 6-13 16-bit peripheral
0x4000_3000 to 0x4000_33FF REF_A Table 6-14 16-bit peripheral
0x4000_3400 to 0x4000_37FF COMP_E0 Table 6-15 16-bit peripheral
0x4000_3800 to 0x4000_3BFF COMP_E1 Table 6-16 16-bit peripheral
0x4000_3C00 to 0x4000_3FFF AES256 Table 6-17 16-bit peripheral
0x4000_4000 to 0x4000_43FF CRC32 Table 6-18 16-bit peripheral
0x4000_4400 to 0x4000_47FF RTC_C Table 6-19 16-bit peripheral
0x4000_4800 to 0x4000_4BFF WDT_A Table 6-20 16-bit peripheral
0x4000_4C00 to 0x4000_4FFF Port Module Table 6-21 16-bit peripheral
0x4000_5000 to 0x4000_53FF Port Mapping Controller Table 6-22 16-bit peripheral
0x4000_5400 to 0x4000_57FF Capacitive Touch I/O 0 Table 6-23 16-bit peripheral
0x4000_5800 to 0x4000_5BFF Capacitive Touch I/O 1 Table 6-24 16-bit peripheral
0x4000_5C00 to 0x4000_8FFF Reserved Read only, always reads 0h
0x4000_9000 to 0x4000_BFFF Reserved Read only, always reads 0h
0x4000_C000 to 0x4000_CFFF Timer32 Table 6-25
0x4000_D000 to 0x4000_DFFF Reserved Read only, always reads 0h
0x4000_E000 to 0x4000_FFFF DMA Table 6-26
0x4001_0000 to 0x4001_03FF PCM Table 6-27
0x4001_0400 to 0x4001_07FF CS Table 6-28
0x4001_0800 to 0x4001_0FFF PSS Table 6-29
0x4001_1000 to 0x4001_17FF FLCTL Table 6-30
0x4001_1800 to 0x4001_1BFF Reserved Read only, always reads 0h
0x4001_1C00 to 0x4001_1FFF Reserved Read only, always reads 0h
0x4001_2000 to 0x4001_23FF Precision ADC Table 6-31
0x4001_2400 to 0x4001_FFFF Reserved Read only, always reads 0h

Table 6-2 Timer_A0 Registers (Base Address: 0x4000_0000)

Timer_A0 Control TA0CTL 00h
Timer_A0 Capture/Compare Control 0 TA0CCTL0 02h
Timer_A0 Capture/Compare Control 1 TA0CCTL1 04h
Timer_A0 Capture/Compare Control 2 TA0CCTL2 06h
Timer_A0 Capture/Compare Control 3 TA0CCTL3 08h
Timer_A0 Capture/Compare Control 4 TA0CCTL4 0Ah
Timer_A0 Counter TA0R 10h
Timer_A0 Capture/Compare 0 TA0CCR0 12h
Timer_A0 Capture/Compare 1 TA0CCR1 14h
Timer_A0 Capture/Compare 2 TA0CCR2 16h
Timer_A0 Capture/Compare 3 TA0CCR3 18h
Timer_A0 Capture/Compare 4 TA0CCR4 1Ah
Timer_A0 Interrupt Vector TA0IV 2Eh
Timer_A0 Expansion 0 TA0EX0 20h

Table 6-3 Timer_A1 Registers (Base Address: 0x4000_0400)

Timer_A1 Control TA1CTL 00h
Timer_A1 Capture/Compare Control 0 TA1CCTL0 02h
Timer_A1 Capture/Compare Control 1 TA1CCTL1 04h
Timer_A1 Capture/Compare Control 2 TA1CCTL2 06h
Timer_A1 Capture/Compare Control 3 TA1CCTL3 08h
Timer_A1 Capture/Compare Control 4 TA1CCTL4 0Ah
Timer_A1 Counter TA1R 10h
Timer_A1 Capture/Compare 0 TA1CCR0 12h
Timer_A1 Capture/Compare 1 TA1CCR1 14h
Timer_A1 Capture/Compare 2 TA1CCR2 16h
Timer_A1 Capture/Compare 3 TA1CCR3 18h
Timer_A1 Capture/Compare 4 TA1CCR4 1Ah
Timer_A1 Interrupt Vector TA1IV 2Eh
Timer_A1 Expansion 0 TA1EX0 20h

Table 6-4 Timer_A2 Registers (Base Address: 0x4000_0800)

Timer_A2 Control TA2CTL 00h
Timer_A2 Capture/Compare Control 0 TA2CCTL0 02h
Timer_A2 Capture/Compare Control 1 TA2CCTL1 04h
Timer_A2 Capture/Compare Control 2 TA2CCTL2 06h
Timer_A2 Capture/Compare Control 3 TA2CCTL3 08h
Timer_A2 Capture/Compare Control 4 TA2CCTL4 0Ah
Timer_A2 Counter TA2R 10h
Timer_A2 Capture/Compare 0 TA2CCR0 12h
Timer_A2 Capture/Compare 1 TA2CCR1 14h
Timer_A2 Capture/Compare 2 TA2CCR2 16h
Timer_A2 Capture/Compare 3 TA2CCR3 18h
Timer_A2 Capture/Compare 4 TA2CCR4 1Ah
Timer_A2 Interrupt Vector TA2IV 2Eh
Timer_A2 Expansion 0 TA2EX0 20h

Table 6-5 Timer_A3 Registers (Base Address: 0x4000_0C00)

Timer_A3 Control TA3CTL 00h
Timer_A3 Capture/Compare Control 0 TA3CCTL0 02h
Timer_A3 Capture/Compare Control 1 TA3CCTL1 04h
Timer_A3 Capture/Compare Control 2 TA3CCTL2 06h
Timer_A3 Capture/Compare Control 3 TA3CCTL3 08h
Timer_A3 Capture/Compare Control 4 TA3CCTL4 0Ah
Timer_A3 Counter TA3R 10h
Timer_A3 Capture/Compare 0 TA3CCR0 12h
Timer_A3 Capture/Compare 1 TA3CCR1 14h
Timer_A3 Capture/Compare 2 TA3CCR2 16h
Timer_A3 Capture/Compare 3 TA3CCR3 18h
Timer_A3 Capture/Compare 4 TA3CCR4 1Ah
Timer_A3 Interrupt Vector TA3IV 2Eh
Timer_A3 Expansion 0 TA3EX0 20h

Table 6-6 eUSCI_A0 Registers (Base Address: 0x4000_1000)

eUSCI_A0 Control Word 0 UCA0CTLW0 00h
eUSCI_A0 Control Word 1 UCA0CTLW1 02h
eUSCI_A0 Baud Rate Control UCA0BRW 06h
eUSCI_A0 Modulation Control UCA0MCTLW 08h
eUSCI_A0 Receive Buffer UCA0RXBUF 0Ch
eUSCI_A0 Transmit Buffer UCA0TXBUF 0Eh
eUSCI_A0 Auto Baud Rate Control UCA0ABCTL 10h
eUSCI_A0 IrDA Control UCA0IRCTL 12h
eUSCI_A0 Interrupt Enable UCA0IE 1Ah
eUSCI_A0 Interrupt Flag UCA0IFG 1Ch
eUSCI_A0 Interrupt Vector UCA0IV 1Eh

Table 6-7 eUSCI_A1 Registers (Base Address: 0x4000_1400)

eUSCI_A1 Control Word 0 UCA1CTLW0 00h
eUSCI_A1 Control Word 1 UCA1CTLW1 02h
eUSCI_A1 Baud Rate Control UCA1BRW 06h
eUSCI_A1 Modulation Control UCA1MCTLW 08h
eUSCI_A1 Receive Buffer UCA1RXBUF 0Ch
eUSCI_A1 Transmit Buffer UCA1TXBUF 0Eh
eUSCI_A1 Auto Baud Rate Control UCA1ABCTL 10h
eUSCI_A1 IrDA Control UCA1IRCTL 12h
eUSCI_A1 Interrupt Enable UCA1IE 1Ah
eUSCI_A1 Interrupt Flag UCA1IFG 1Ch
eUSCI_A1 Interrupt Vector UCA1IV 1Eh

Table 6-8 eUSCI_A2 Registers (Base Address: 0x4000_1800)

eUSCI_A2 Control Word 0 UCA2CTLW0 00h
eUSCI_A2 Control Word 1 UCA2CTLW1 02h
eUSCI_A2 Baud Rate Control UCA2BRW 06h
eUSCI_A2 Modulation Control UCA2MCTLW 08h
eUSCI_A2 Receive Buffer UCA2RXBUF 0Ch
eUSCI_A2 Transmit Buffer UCA2TXBUF 0Eh
eUSCI_A2 Auto Baud Rate Control UCA2ABCTL 10h
eUSCI_A2 IrDA Control UCA2IRCTL 12h
eUSCI_A2 Interrupt Enable UCA2IE 1Ah
eUSCI_A2 Interrupt Flag UCA2IFG 1Ch
eUSCI_A2 Interrupt Vector UCA2IV 1Eh

Table 6-9 eUSCI_A3 Registers (Base Address: 0x4000_1C00)

eUSCI_A3 Control Word 0 UCA3CTLW0 00h
eUSCI_A3 Control Word 1 UCA3CTLW1 02h
eUSCI_A3 Baud Rate Control UCA3BRW 06h
eUSCI_A3 Modulation Control UCA3MCTLW 08h
eUSCI_A3 Receive Buffer UCA3RXBUF 0Ch
eUSCI_A3 Transmit Buffer UCA3TXBUF 0Eh
eUSCI_A3 Auto Baud Rate Control UCA3ABCTL 10h
eUSCI_A3 IrDA Control UCA3IRCTL 12h
eUSCI_A3 Interrupt Enable UCA3IE 1Ah
eUSCI_A3 Interrupt Flag UCA3IFG 1Ch
eUSCI_A3 Interrupt Vector UCA3IV 1Eh

Table 6-10 eUSCI_B0 Registers (Base Address: 0x4000_2000)

eUSCI_B0 Control Word 0 UCB0CTLW0 00h
eUSCI_B0 Control Word 1 UCB0CTLW1 02h
eUSCI_B0 Bit Rate Control Word UCB0BRW 06h
eUSCI_B0 Status Word UCB0STATW 08h
eUSCI_B0 Byte Counter Threshold UCB0TBCNT 0Ah
eUSCI_B0 Receive Buffer UCB0RXBUF 0Ch
eUSCI_B0 Transmit Buffer UCB0TXBUF 0Eh
eUSCI_B0 I2C Own Address 0 UCB0I2COA0 14h
eUSCI_B0 I2C Own Address 1 UCB0I2COA1 16h
eUSCI_B0 I2C Own Address 2 UCB0I2COA2 18h
eUSCI_B0 I2C Own Address 3 UCB0I2COA3 1Ah
eUSCI_B0 Received Address UCB0ADDRX 1Ch
eUSCI_B0 Address Mask UCB0ADDMASK 1Eh
eUSCI_B0 I2C Slave Address UCB0I2CSA 20h
eUSCI_B0 Interrupt Enable UCB0IE 2Ah
eUSCI_B0 Interrupt Flag UCB0IFG 2Ch
eUSCI_B0 Interrupt Vector UCB0IV 2Eh

Table 6-11 eUSCI_B1 Registers (Base Address: 0x4000_2400)

eUSCI_B1 Control Word 0 UCB1CTLW0 00h
eUSCI_B1 Control Word 1 UCB1CTLW1 02h
eUSCI_B1 Bit Rate Control Word UCB1BRW 06h
eUSCI_B1 Status Word UCB1STATW 08h
eUSCI_B1 Byte Counter Threshold UCB1TBCNT 0Ah
eUSCI_B1 Receive Buffer UCB1RXBUF 0Ch
eUSCI_B1 Transmit Buffer UCB1TXBUF 0Eh
eUSCI_B1 I2C Own Address 0 UCB1I2COA0 14h
eUSCI_B1 I2C Own Address 1 UCB1I2COA1 16h
eUSCI_B1 I2C Own Address 2 UCB1I2COA2 18h
eUSCI_B1 I2C Own Address 3 UCB1I2COA3 1Ah
eUSCI_B1 Received Address UCB1ADDRX 1Ch
eUSCI_B1 Address Mask UCB1ADDMASK 1Eh
eUSCI_B1 I2C Slave Address UCB1I2CSA 20h
eUSCI_B1 Interrupt Enable UCB1IE 2Ah
eUSCI_B1 Interrupt Flag UCB1IFG 2Ch
eUSCI_B1 Interrupt Vector UCB1IV 2Eh

Table 6-12 eUSCI_B2 Registers (Base Address: 0x4000_2800)

eUSCI_B2 Control Word 0 UCB2CTLW0 00h
eUSCI_B2 Control Word 1 UCB2CTLW1 02h
eUSCI_B2 Bit Rate Control Word UCB2BRW 06h
eUSCI_B2 Status Word UCB2STATW 08h
eUSCI_B2 Byte Counter Threshold UCB2TBCNT 0Ah
eUSCI_B2 Receive Buffer UCB2RXBUF 0Ch
eUSCI_B2 Transmit Buffer UCB2TXBUF 0Eh
eUSCI_B2 I2C Own Address 0 UCB2I2COA0 14h
eUSCI_B2 I2C Own Address 1 UCB2I2COA1 16h
eUSCI_B2 I2C Own Address 2 UCB2I2COA2 18h
eUSCI_B2 I2C Own Address 3 UCB2I2COA3 1Ah
eUSCI_B2 Received Address UCB2ADDRX 1Ch
eUSCI_B2 Address Mask UCB2ADDMASK 1Eh
eUSCI_B2 I2C Slave Address UCB2I2CSA 20h
eUSCI_B2 Interrupt Enable UCB2IE 2Ah
eUSCI_B2 Interrupt Flag UCB2IFG 2Ch
eUSCI_B2 Interrupt Vector UCB2IV 2Eh

Table 6-13 eUSCI_B3 Registers (Base Address: 0x4000_2C00)

eUSCI_B3 Control Word 0 UCB3CTLW0 00h
eUSCI_B3 Control Word 1 UCB3CTLW1 02h
eUSCI_B3 Bit Rate Control Word UCB3BRW 06h
eUSCI_B3 Status Word UCB3STATW 08h
eUSCI_B3 Byte Counter Threshold UCB3TBCNT 0Ah
eUSCI_B3 Receive Buffer UCB3RXBUF 0Ch
eUSCI_B3 Transmit Buffer UCB3TXBUF 0Eh
eUSCI_B3 I2C Own Address 0 UCB3I2COA0 14h
eUSCI_B3 I2C Own Address 1 UCB3I2COA1 16h
eUSCI_B3 I2C Own Address 2 UCB3I2COA2 18h
eUSCI_B3 I2C Own Address 3 UCB3I2COA3 1Ah
eUSCI_B3 Received Address UCB3ADDRX 1Ch
eUSCI_B3 Address Mask UCB3ADDMASK 1Eh
eUSCI_B3 I2C Slave Address UCB3I2CSA 20h
eUSCI_B3 Interrupt Enable UCB3IE 2Ah
eUSCI_B3 Interrupt Flag UCB3IFG 2Ch
eUSCI_B3 Interrupt Vector UCB3IV 2Eh

Table 6-14 REF_A Registers (Base Address: 0x4000_3000)

REF_A Control 0 REFCTL0 00h

Table 6-15 COMP_E0 Registers (Base Address: 0x4000_3400)

Comparator_E0 Control 0 CE0CTL0 00h
Comparator_E0 Control 1 CE0CTL1 02h
Comparator_E0 Control 2 CE0CTL2 04h
Comparator_E0 Control 3 CE0CTL3 06h
Comparator_E0 Interrupt CE0INT 0Ch
Comparator_E0 Interrupt Vector Word CE0IV 0Eh

Table 6-16 COMP_E1 Registers (Base Address: 0x4000_3800)

Comparator_E1 Control 0 CE1CTL0 00h
Comparator_E1 Control 1 CE1CTL1 02h
Comparator_E1 Control 2 CE1CTL2 04h
Comparator_E1 Control 3 CE1CTL3 06h
Comparator_E1 Interrupt CE1INT 0Ch
Comparator_E1 Interrupt Vector Word CE1IV 0Eh

Table 6-17 AES256 Registers (Base Address: 0x4000_3C00)

AES Accelerator Control 0 AESACTL0 00h
AES Accelerator Control 1 AESACTL1 02h
AES Accelerator Status AESASTAT 04h
AES Accelerator Key AESAKEY 06h
AES Accelerator Data In AESADIN 08h
AES Accelerator Data Out AESADOUT 0Ah
AES Accelerator XORed Data In AESAXDIN 0Ch
AES Accelerator XORed Data In (no trigger) AESAXIN 0Eh

Table 6-18 CRC32 Registers (Base Address: 0x4000_4000)

CRC32 Data Input Low CRC32DI 000h
CRC32 Data In Reverse Low CRC32DIRB 004h
CRC32 Initialization and Result Low CRC32INIRES_LO 008h
CRC32 Initialization and Result High CRC32INIRES_HI 00Ah
CRC32 Result Reverse Low CRC32RESR_LO 00Ch
CRC32 Result Reverse High CRC32RESR_HI 00Eh
CRC16 Data Input Low CRC16DI 010h
CRC16 Data In Reverse Low CRC16DIRB 014h
CRC16 Initialization and Result CRC16INIRES 018h
CRC16 Result Reverse CRC16RESR 01Eh

Table 6-19 RTC_C Registers (Base Address: 0x4000_4400)

Real-Time Clock Control 0 RTCCTL0 00h
Real-Time Clock Control 1, 3 RTCCTL13 02h
Real-Time Clock Offset Calibration RTCOCAL 04h
Real-Time Clock Temperature Compensation RTCTCMP 06h
Real-Time Prescale Timer 0 Control RTCPS0CTL 08h
Real-Time Prescale Timer 1 Control RTCPS1CTL 0Ah
Real-Time Prescale Timer 0, 1 Counter RTCPS 0Ch
Real Time Clock Interrupt Vector RTCIV 0Eh
Real-Time Clock Seconds, Minutes RTCTIM0 10h
Real-Time Clock Hour, Day of Week RTCTIM1 12h
Real-Time Clock Date RTCDATE 14h
Real-Time Clock Year RTCYEAR 16h
Real-Time Clock Minutes, Hour Alarm RTCAMINHR 18h
Real-Time Clock Day of Week, Day of Month Alarm RTCADOWDAY 1Ah
Binary-to-BCD Conversion RTCBIN2BCD 1Ch
BCD-to-Binary Conversion RTCBCD2BIN 1Eh

Table 6-20 WDT_A Registers (Base Address: 0x4000_4800)

Watchdog Timer Control WDTCTL 0Ch

Table 6-21 Port Registers (Base Address: 0x4000_4C00)

Port 1 Input P1IN 000h
Port 2 Input P2IN 001h
Port 1 Output P1OUT 002h
Port 2 Output P2OUT 003h
Port 1 Direction P1DIR 004h
Port 2 Direction P2DIR 005h
Port 1 Resistor Enable P1REN 006h
Port 2 Resistor Enable P2REN 007h
Port 2 Drive Strength P2DS 009h
Port 1 Select 0 P1SEL0 00Ah
Port 2 Select 0 P2SEL0 00Bh
Port 1 Select 1 P1SEL1 00Ch
Port 2 Select 1 P2SEL1 00Dh
Port 1 Interrupt Vector P1IV 00Eh
Port 1 Complement Selection P1SELC 016h
Port 2 Complement Selection P2SELC 017h
Port 1 Interrupt Edge Select P1IES 018h
Port 2 Interrupt Edge Select P2IES 019h
Port 1 Interrupt Enable P1IE 01Ah
Port 2 Interrupt Enable P2IE 01Bh
Port 1 Interrupt Flag P1IFG 01Ch
Port 2 Interrupt Flag P2IFG 01Dh
Port 2 Interrupt Vector P2IV 01Eh
Port 3 Input P3IN 020h
Port 4 Input P4IN 021h
Port 3 Output P3OUT 022h
Port 4 Output P4OUT 023h
Port 3 Direction P3DIR 024h
Port 4 Direction P4DIR 025h
Port 3 Resistor Enable P3REN 026h
Port 4 Resistor Enable P4REN 027h
Port 3 Select 0 P3SEL0 02Ah
Port 4 Select 0 P4SEL0 02Bh
Port 3 Select 1 P3SEL1 02Ch
Port 4 Select 1 P4SEL1 02Dh
Port 3 Interrupt Vector P3IV 02Eh
Port 3 Complement Selection P3SELC 036h
Port 4 Complement Selection P4SELC 037h
Port 3 Interrupt Edge Select P3IES 038h
Port 4 Interrupt Edge Select P4IES 039h
Port 3 Interrupt Enable P3IE 03Ah
Port 4 Interrupt Enable P4IE 03Bh
Port 3 Interrupt Flag P3IFG 03Ch
Port 4 Interrupt Flag P4IFG 03Dh
Port 4 Interrupt Vector P4IV 03Eh
Port 5 Input P5IN 040h
Port 6 Input P6IN 041h
Port 5 Output P5OUT 042h
Port 6 Output P6OUT 043h
Port 5 Direction P5DIR 044h
Port 6 Direction P6DIR 045h
Port 5 Resistor Enable P5REN 046h
Port 6 Resistor Enable P6REN 047h
Port 5 Select 0 P5SEL0 04Ah
Port 6 Select 0 P6SEL0 04Bh
Port 5 Select 1 P5SEL1 04Ch
Port 6 Select 1 P6SEL1 04Dh
Port 5 Interrupt Vector P5IV 04Eh
Port 5 Complement Selection P5SELC 056h
Port 6 Complement Selection P6SELC 057h
Port 5 Interrupt Edge Select P5IES 058h
Port 6 Interrupt Edge Select P6IES 059h
Port 5 Interrupt Enable P5IE 05Ah
Port 6 Interrupt Enable P6IE 05Bh
Port 5 Interrupt Flag P5IFG 05Ch
Port 6 Interrupt Flag P6IFG 05Dh
Port 6 Interrupt Vector P6IV 05Eh
Port 7 Input P7IN 060h
Port 8 Input P8IN 061h
Port 7 Output P7OUT 062h
Port 8 Output P8OUT 063h
Port 7 Direction P7DIR 064h
Port 8 Direction P8DIR 065h
Port 7 Resistor Enable P7REN 066h
Port 8 Resistor Enable P8REN 067h
Port 7 Select 0 P7SEL0 06Ah
Port 8 Select 0 P8SEL0 06Bh
Port 7 Select 1 P7SEL1 06Ch
Port 8 Select 1 P8SEL1 06Dh
Port 7 Complement Selection P7SELC 076h
Port 8 Complement Selection P8SELC 077h
Port 9 Input P9IN 080h
Port 10 Input P10IN 081h
Port 9 Output P9OUT 082h
Port 10 Output P10OUT 083h
Port 9 Direction P9DIR 084h
Port 10 Direction P10DIR 085h
Port 9 Resistor Enable P9REN 086h
Port 10 Resistor Enable P10REN 087h
Port 9 Select 0 P9SEL0 08Ah
Port 10 Select 0 P10SEL0 08Bh
Port 9 Select 1 P9SEL1 08Ch
Port 10 Select 1 P10SEL1 08Dh
Port 9 Complement Selection P9SELC 096h
Port 10 Complement Selection P10SELC 097h
Port J Input PJIN 120h
Port J Output PJOUT 122h
Port J Direction PJDIR 124h
Port J Resistor Enable PJREN 126h
Port J Select 0 PJSEL0 12Ah
Port J Select 1 PJSEL1 12Ch
Port J Complement Select PJSELC 136h

Table 6-22 PMAP Registers (Base Address: 0x4000_5000)

Port Mapping Key PMAPKEYID 00h
Port Mapping Control PMAPCTL 02h
Port Mapping P2.0 P2MAP0 10h
Port Mapping P2.1 P2MAP1 11h
Port Mapping P2.2 P2MAP2 12h
Port Mapping P2.3 P2MAP3 13h
Port Mapping P2.4 P2MAP4 14h
Port Mapping P2.5 P2MAP5 15h
Port Mapping P2.6 P2MAP6 16h
Port Mapping P2.7 P2MAP7 17h
Port Mapping P3.0 P3MAP0 18h
Port Mapping P3.1 P3MAP1 19h
Port Mapping P3.2 P3MAP2 1Ah
Port Mapping P3.3 P3MAP3 1Bh
Port Mapping P3.4 P3MAP4 1Ch
Port Mapping P3.5 P3MAP5 1Dh
Port Mapping P3.6 P3MAP6 1Eh
Port Mapping P3.7 P3MAP7 1Fh
Port Mapping P7.0 P7MAP0 38h
Port Mapping P7.1 P7MAP1 39h
Port Mapping P7.2 P7MAP2 3Ah
Port Mapping P7.3 P7MAP3 3Bh
Port Mapping P7.4 P7MAP4 3Ch
Port Mapping P7.5 P7MAP5 3Dh
Port Mapping P7.6 P7MAP6 3Eh
Port Mapping P7.7 P7MAP7 3Fh

Table 6-23 Capacitive Touch I/O 0 Registers (Base Address: 0x4000_5400)

Capacitive Touch I/O 0 Control CAPTIO0CTL 0Eh

Table 6-24 Capacitive Touch I/O 1 Registers (Base Address: 0x4000_5800)

Capacitive Touch I/O 1 Control CAPTIO1CTL 0Eh

Table 6-25 Timer32 Registers (Base Address: 0x4000_C000)

Timer 1 Load T32LOAD1 00h
Timer 1 Current Value T32VALUE1 04h
Timer 1 Timer Control T32CONTROL1 08h
Timer 1 Interrupt Clear T32INTCLR1 0Ch
Timer 1 Raw Interrupt Status T32RIS1 10h
Timer 1 Interrupt Status T32MIS1 14h
Timer 1 Background Load T32BGLOAD1 18h
Timer 2 Load T32LOAD2 20h
Timer 2 Current Value T32VALUE2 24h
Timer 2 Timer Control T32CONTROL2 28h
Timer 2 Interrupt Clear T32INTCLR2 2Ch
Timer 2 Raw Interrupt Status T32RIS2 30h
Timer 2 Interrupt Status T32MIS2 34h
Timer 2 Background Load T32BGLOAD2 38h

Table 6-26 DMA Registers (Base Address: 0x4000_E000)

Device Configuration Status DMA_DEVICE_CFG 000h
Software Channel Trigger DMA_SW_CHTRIG 004h
Channel 0 Source Configuration DMA_CH0_SRCCFG 010h
Channel 1 Source Configuration DMA_CH1_SRCCFG 014h
Channel 2 Source Configuration DMA_CH2_SRCCFG 018h
Channel 3 Source Configuration DMA_CH3_SRCCFG 01Ch
Channel 4 Source Configuration DMA_CH4_SRCCFG 020h
Channel 5 Source Configuration DMA_CH5_SRCCFG 024h
Channel 6 Source Configuration DMA_CH6_SRCCFG 028h
Channel 7 Source Configuration DMA_CH7_SRCCFG 02Ch
Interrupt 1 Source Channel Configuration DMA_INT1_SRCCFG 100h
Interrupt 2 Source Channel Configuration DMA_INT2_SRCCFG 104h
Interrupt 3 Source Channel Configuration DMA_INT3_SRCCFG 108h
Interrupt 0 Source Channel Flag DMA_INT0_SRCFLG 110h
Interrupt 0 Source Channel Clear Flag DMA_INT0_CLRFLG 114h
Status DMA_STAT 1000h
Configuration DMA_CFG 1004h
Channel Control Data Base Pointer DMA_CTLBASE 1008h
Channel Alternate Control Data Base Pointer DMA_ALTBASE 100Ch
Channel Wait on Request Status DMA_WAITSTAT 1010h
Channel Software Request DMA_SWREQ 1014h
Channel Useburst Set DMA_USEBURSTSET 1018h
Channel Useburst Clear DMA_USEBURSTCLR 101Ch
Channel Request Mask Set DMA_REQMASKSET 1020h
Channel Request Mask Clear DMA_REQMASKCLR 1024h
Channel Enable Set DMA_ENASET 1028h
Channel Enable Clear DMA_ENACLR 102Ch
Channel Primary-Alternate Set DMA_ALTSET 1030h
Channel Primary-Alternate Clear DMA_ALTCLR 1034h
Channel Priority Set DMA_PRIOSET 1038h
Channel Priority Clear DMA_PRIOCLR 103Ch
Bus Error Clear DMA_ERRCLR 104Ch

Table 6-27 PCM Registers (Base Address: 0x4001_0000)

Control 0 PCMCTL0 00h
Control 1 PCMCTL1 04h
Interrupt Enable PCMIE 08h
Interrupt Flag PCMIFG 0Ch
Clear Interrupt Flag PCMCLRIFG 10h

Table 6-28 CS Registers (Base Address: 0x4001_0400)

Key CSKEY 00h
Control 0 CSCTL0 04h
Control 1 CSCTL1 08h
Control 2 CSCTL2 0Ch
Control 3 CSCTL3 10h
Clock Enable CSCLKEN 30h
Status CSSTAT 34h
Interrupt Enable CSIE 40h
Interrupt Flag CSIFG 48h
Clear Interrupt Flag CSCLRIFG 50h
Set Interrupt Flag CSSETIFG 58h
DCO External Resistor Calibration 0 CSDCOERCAL0 60h
DCO External Resistor Calibration 1 CSDCOERCAL1 64h

Table 6-29 PSS Registers (Base Address: 0x4001_0800)

Key PSSKEY 00h
Control 0 PSSCTL0 04h
Interrupt Enable PSSIE 34h
Interrupt Flag PSSIFG 38h
Clear Interrupt Flag PSSCLRIFG 3Ch

Table 6-30 FLCTL Registers (Base Address: 0x4001_1000)

Power Status FLCTL_POWER_STAT 000h
Bank 0 Read Control FLCTL_BANK0_RDCTL 010h
Bank 1 Read Control FLCTL_BANK1_RDCTL 014h
Read Burst/Compare Control and Status FLCTL_RDBRST_CTLSTAT 020h
Read Burst/Compare Start Address FLCTL_RDBRST_STARTADDR 024h
Read Burst/Compare Length FLCTL_RDBRST_LEN 028h
Read Burst/Compare Fail Address FLCTL_RDBRST_FAILADDR 03Ch
Read Burst/Compare Fail Count FLCTL_RDBRST_FAILCNT 040h
Program Control and Status FLCTL_PRG_CTLSTAT 050h
Program Burst Control and Status FLCTL_PRGBRST_CTLSTAT 054h
Program Burst Start Address FLCTL_PRGBRST_STARTADDR 058h
Program Burst Data0 0 FLCTL_PRGBRST_DATA0_0 060h
Program Burst Data0 1 FLCTL_PRGBRST_DATA0_1 064h
Program Burst Data0 2 FLCTL_PRGBRST_DATA0_2 068h
Program Burst Data0 3 FLCTL_PRGBRST_DATA0_3 06Ch
Program Burst Data1 0 FLCTL_PRGBRST_DATA1_0 070h
Program Burst Data1 1 FLCTL_PRGBRST_DATA1_1 074h
Program Burst Data1 2 FLCTL_PRGBRST_DATA1_2 078h
Program Burst Data1 3 FLCTL_PRGBRST_DATA1_3 07Ch
Program Burst Data2 0 FLCTL_PRGBRST_DATA2_0 080h
Program Burst Data2 1 FLCTL_PRGBRST_DATA2_1 084h
Program Burst Data2 2 FLCTL_PRGBRST_DATA2_2 088h
Program Burst Data2 3 FLCTL_PRGBRST_DATA2_3 08Ch
Program Burst Data3 0 FLCTL_PRGBRST_DATA3_0 090h
Program Burst Data3 1 FLCTL_PRGBRST_DATA3_1 094h
Program Burst Data3 2 FLCTL_PRGBRST_DATA3_2 098h
Program Burst Data3 3 FLCTL_PRGBRST_DATA3_3 09Ch
Erase Control and Status FLCTL_ERASE_CTLSTAT 0A0h
Erase Sector Address FLCTL_ERASE_SECTADDR 0A4h
Information Memory Bank 0 Write/Erase Protection FLCTL_BANK0_INFO_WEPROT 0B0h
Main Memory Bank 0 Write/Erase Protection FLCTL_BANK0_MAIN_WEPROT 0B4h
Information Memory Bank 1 Write/Erase Protection FLCTL_BANK1_INFO_WEPROT 0C0h
Main Memory Bank 1 Write/Erase Protection FLCTL_BANK1_MAIN_WEPROT 0C4h
Benchmark Control and Status FLCTL_BMRK_CTLSTAT 0D0h
Benchmark Instruction Fetch Count FLCTL_BMRK_IFETCH 0D4h
Benchmark Data Read Count FLCTL_BMRK_DREAD 0D8h
Benchmark Count Compare FLCTL_BMRK_CMP 0DCh
Interrupt Flag FLCTL_IFG 0F0h
Interrupt Enable FLCTL_IE 0F4h
Clear Interrupt Flag FLCTL_CLRIFG 0F8h
Set Interrupt Flag FLCTL_SETIFG 0FCh
Read Timing Control FLCTL_READ_TIMCTL 100h
Read Margin Timing Control FLCTL_READMARGIN_TIMCTL 104h
Program Verify Timing Control FLCTL_PRGVER_TIMCTL 108h
Erase Verify Timing Control FLCTL_ERSVER_TIMCTL 10Ch
Program Timing Control FLCTL_PROGRAM_TIMCTL 114h
Erase Timing Control FLCTL_ERASE_TIMCTL 118h
Mass Erase Timing Control FLCTL_MASSERASE_TIMCTL 11Ch
Burst Program Timing Control FLCTL_BURSTPRG_TIMCTL 120h

Table 6-31 Precision ADC Registers (Base Address: 0x4001_2000)

Control 0 ADC14CTL0 00h
Control 1 ADC14CTL1 04h
Window Comparator Low Threshold 0 ADC14LO0 08h
Window Comparator High Threshold 0 ADC14HI0 0Ch
Window Comparator Low Threshold 1 ADC14LO1 10h
Window Comparator High Threshold 1 ADC14HI1 14h
Memory Control 0 ADC14MCTL0 18h
Memory Control 1 ADC14MCTL1 1Ch
Memory Control 2 ADC14MCTL2 20h
Memory Control 3 ADC14MCTL3 24h
Memory Control 4 ADC14MCTL4 28h
Memory Control 5 ADC14MCTL5 2Ch
Memory Control 6 ADC14MCTL6 30h
Memory Control 7 ADC14MCTL7 34h
Memory Control 8 ADC14MCTL8 38h
Memory Control 9 ADC14MCTL9 3Ch
Memory Control 10 ADC14MCTL10 40h
Memory Control 11 ADC14MCTL11 44h
Memory Control 12 ADC14MCTL12 48h
Memory Control 13 ADC14MCTL13 4Ch
Memory Control 14 ADC14MCTL14 50h
Memory Control 15 ADC14MCTL15 54h
Memory Control 16 ADC14MCTL16 58h
Memory Control 17 ADC14MCTL17 5Ch
Memory Control 18 ADC14MCTL18 60h
Memory Control 19 ADC14MCTL19 64h
Memory Control 20 ADC14MCTL20 68h
Memory Control 21 ADC14MCTL21 6Ch
Memory Control 22 ADC14MCTL22 70h
Memory Control 23 ADC14MCTL23 74h
Memory Control 24 ADC14MCTL24 78h
Memory Control 25 ADC14MCTL25 7Ch
Memory Control 26 ADC14MCTL26 80h
Memory Control 27 ADC14MCTL27 84h
Memory Control 28 ADC14MCTL28 88h
Memory Control 29 ADC14MCTL29 8Ch
Memory Control 30 ADC14MCTL30 90h
Memory Control 31 ADC14MCTL31 94h
Memory 0 ADC14MEM0 98h
Memory 1 ADC14MEM1 9Ch
Memory 2 ADC14MEM2 A0h
Memory 3 ADC14MEM3 A4h
Memory 4 ADC14MEM4 A8h
Memory 5 ADC14MEM5 ACh
Memory 6 ADC14MEM6 B0h
Memory 7 ADC14MEM7 B4h
Memory 8 ADC14MEM8 B8h
Memory 9 ADC14MEM9 BCh
Memory 10 ADC14MEM10 C0h
Memory 11 ADC14MEM11 C4h
Memory 12 ADC14MEM12 C8h
Memory 13 ADC14MEM13 CCh
Memory 14 ADC14MEM14 D0h
Memory 15 ADC14MEM15 D4h
Memory 16 ADC14MEM16 D8h
Memory 17 ADC14MEM17 DCh
Memory 18 ADC14MEM18 E0h
Memory 19 ADC14MEM19 E4h
Memory 20 ADC14MEM20 E8h
Memory 21 ADC14MEM21 ECh
Memory 22 ADC14MEM22 F0h
Memory 23 ADC14MEM23 F4h
Memory 24 ADC14MEM24 F8h
Memory 25 ADC14MEM25 FCh
Memory 26 ADC14MEM26 100
Memory 27 ADC14MEM27 104
Memory 28 ADC14MEM28 108
Memory 29 ADC14MEM29 10C
Memory 30 ADC14MEM30 110h
Memory 31 ADC14MEM31 114h
Interrupt Enable 0 ADC14IER0 13Ch
Interrupt Enable 1 ADC14IER1 140h
Interrupt Flag 0 ADC14IFGR0 144h
Interrupt Flag 1 ADC14IFGR1 148h
Clear Interrupt Flag 0 ADC14CLRIFGR0 14Ch
Clear Interrupt Flag 1 ADC14CLRIFGR1 150h
Interrupt Vector ADC14IV 154h