SLAS826H March   2015  – June 2019 MSP432P401M , MSP432P401R

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. Table 4-2 Signal Descriptions
    4. 4.4 Pin Multiplexing
    5. 4.5 Buffer Types
    6. 4.6 Connection for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Recommended External Components
    5. 5.5  Operating Mode VCC Ranges
    6. 5.6  Operating Mode CPU Frequency Ranges
    7. 5.7  Operating Mode Peripheral Frequency Ranges
    8. 5.8  Operating Mode Execution Frequency vs Flash Wait-State Requirements
    9. 5.9  Current Consumption During Device Reset of the 100-pin LQFP Package
    10. 5.10 Current Consumption in LDO-Based Active Modes – Dhrystone 2.1 Program
    11. 5.11 Current Consumption in DC-DC-Based Active Modes – Dhrystone 2.1 Program
    12. 5.12 Current Consumption in Low-Frequency Active Modes – Dhrystone 2.1 Program
    13. 5.13 Typical Characteristics of Active Mode Currents for CoreMark Program
    14. 5.14 Typical Characteristics of Active Mode Currents for Prime Number Program
    15. 5.15 Typical Characteristics of Active Mode Currents for Fibonacci Program
    16. 5.16 Typical Characteristics of Active Mode Currents for While(1) Program
    17. 5.17 Typical Characteristics of Low-Frequency Active Mode Currents for CoreMark Program
    18. 5.18 Current Consumption in LDO-Based LPM0 Modes
    19. 5.19 Current Consumption in DC-DC-Based LPM0 Modes
    20. 5.20 Current Consumption in Low-Frequency LPM0 Modes
    21. 5.21 Current Consumption in LPM3, LPM4 Modes
    22. 5.22 Current Consumption in LPM3.5, LPM4.5 Modes
    23. 5.23 Current Consumption of Digital Peripherals
    24. 5.24 Thermal Resistance Characteristics
    25. 5.25 Timing and Switching Characteristics
      1. 5.25.1  Reset Timing
        1. Table 5-1 Reset Recovery Latencies
        2. Table 5-2 External Reset Recovery Latencies
      2. 5.25.2  Peripheral Register Access Timing
        1. Table 5-3 Peripheral Register Access Latency
      3. 5.25.3  Mode Transition Timing
        1. Table 5-4 Active Mode Transition Latencies
        2. Table 5-5 LPM0 Mode Transition Latencies
        3. Table 5-6 LPM3, LPM4 Mode Transition Latencies
        4. Table 5-7 LPM3.5, LPM4.5 Mode Transition Latencies
      4. 5.25.4  Clock Specifications
        1. Table 5-8  Low-Frequency Crystal Oscillator, LFXT, Recommended Operating Conditions
        2. Table 5-9  Low-Frequency Crystal Oscillator, LFXT
        3. Table 5-10 High-Frequency Crystal Oscillator, HFXT, Recommended Operating Conditions
        4. Table 5-11 High-Frequency Crystal Oscillator, HFXT
        5. Table 5-12 DCO
        6. Table 5-13 DCO Overall Tolerance
        7. Table 5-14 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        8. Table 5-15 Internal-Reference Low-Frequency Oscillator (REFO) in 32.768-kHz Mode
        9. Table 5-16 Internal-Reference Low-Frequency Oscillator (REFO) in 128-kHz Mode
        10. Table 5-17 Module Oscillator (MODOSC)
        11. Table 5-18 System Oscillator (SYSOSC)
      5. 5.25.5  Power Supply System
        1. Table 5-19 VCORE Regulator (LDO) Characteristics
        2. Table 5-20 VCORE Regulator (DC-DC) Characteristics
        3. Table 5-21 PSS, VCCDET
        4. Table 5-22 PSS, SVSMH
      6. 5.25.6  Digital I/Os
        1. Table 5-23 Digital Inputs (Applies to Both Normal and High-Drive I/Os)
        2. Table 5-24 Digital Outputs, Normal I/Os
        3. Table 5-25 Digital Outputs, High-Drive I/Os
        4. Table 5-26 Pin-Oscillator Frequency, Ports Px
        5. 5.25.6.1   Typical Characteristics, Normal-Drive I/O Outputs at 3.0 V and 2.2 V
        6. 5.25.6.2   Typical Characteristics, High-Drive I/O Outputs at 3.0 V and 2.2 V
        7. 5.25.6.3   Typical Characteristics, Pin-Oscillator Frequency
      7. 5.25.7  Precision ADC
        1. Table 5-27 Precision ADC, Power Supply and Input Range Conditions
        2. Table 5-28 Precision ADC, Timing Parameters
        3. Table 5-29 Precision ADC, Linearity Parameters
        4. Table 5-30 Precision ADC, Dynamic Parameters
        5. Table 5-31 Precision ADC, Temperature Sensor and Built-In V1/2
        6. Table 5-32 Precision ADC, Internal Reference Buffers
        7. Table 5-33 Precision ADC, External Reference
        8. 5.25.7.1   Typical Characteristics of ADC
      8. 5.25.8  REF_A
        1. Table 5-34 REF_A, Built-In Reference (LDO Operation)
      9. 5.25.9  Comparator_E
        1. Table 5-35 Comparator_E
      10. 5.25.10 eUSCI
        1. Table 5-36 eUSCI Clock Frequency (UART Mode)
        2. Table 5-37 eUSCI Switching Characteristics (UART Mode)
        3. Table 5-38 eUSCI Clock Frequency (SPI Master Mode)
        4. Table 5-39 eUSCI Switching Characteristics (SPI Master Mode)
        5. Table 5-40 eUSCI Switching Characteristics (SPI Slave Mode)
        6. Table 5-41 eUSCI Clock Frequency (I2C Mode)
        7. Table 5-42 eUSCI Switching Characteristics (I2C Mode)
      11. 5.25.11 Timers
        1. Table 5-43 Timer_A
        2. Table 5-44 Timer32
      12. 5.25.12 Memories
        1. Table 5-45 Flash Memory
        2. Table 5-46 Flash Operations Using MSP432 Peripheral Driver Libraries
        3. Table 5-47 Flash Stand-Alone Operations
        4. Table 5-48 SRAM
      13. 5.25.13 Emulation and Debug
        1. Table 5-49 JTAG
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  Processor and Execution Features
      1. 6.2.1 Floating-Point Unit
      2. 6.2.2 Memory Protection Unit
      3. 6.2.3 Nested Vectored Interrupt Controller (NVIC)
      4. 6.2.4 SysTick
      5. 6.2.5 Debug and Trace Features
    3. 6.3  Memory Map
      1. 6.3.1 Code Zone Memory Map
        1. 6.3.1.1 Flash Memory Region
        2. 6.3.1.2 SRAM Region
        3. 6.3.1.3 ROM Region
      2. 6.3.2 SRAM Zone Memory Map
        1. 6.3.2.1 SRAM Region
        2. 6.3.2.2 SRAM Bit-Band Alias Region
      3. 6.3.3 Peripheral Zone Memory Map
        1. 6.3.3.1 Peripheral Region
        2. 6.3.3.2 Peripheral Bit Band Alias Region
      4. 6.3.4 Debug and Trace Peripheral Zone
    4. 6.4  Memories on the MSP432P401x
      1. 6.4.1 Flash Memory
        1. 6.4.1.1 Flash Main Memory (0x0000_0000 to 0x0003_FFFF)
        2. 6.4.1.2 Flash Information Memory (0x0020_0000 to 0x0020_3FFF)
        3. 6.4.1.3 Flash Operation
      2. 6.4.2 SRAM
        1. 6.4.2.1 SRAM Bank Enable Configuration
        2. 6.4.2.2 SRAM Bank Retention Configuration and Backup Memory
      3. 6.4.3 ROM
    5. 6.5  DMA
      1. 6.5.1 DMA Source Mapping
      2. 6.5.2 DMA Completion Interrupts
      3. 6.5.3 DMA Access Privileges
    6. 6.6  Memory Map Access Details
      1. 6.6.1 Master and Slave Access Priority Settings
      2. 6.6.2 Memory Map Access Response
    7. 6.7  Interrupts
      1. 6.7.1 NMI
      2. 6.7.2 Device-Level User Interrupts
    8. 6.8  System Control
      1. 6.8.1 Device Resets
        1. 6.8.1.1 Power On/Off Reset (POR)
        2. 6.8.1.2 Reboot Reset
        3. 6.8.1.3 Hard Reset
        4. 6.8.1.4 Soft Reset
      2. 6.8.2 Power Supply System (PSS)
        1. 6.8.2.1 VCCDET
        2. 6.8.2.2 Supply Supervisor and Monitor for High Side (SVSMH)
        3. 6.8.2.3 Core Voltage Regulator
      3. 6.8.3 Power Control Manager (PCM)
      4. 6.8.4 Clock System (CS)
        1. 6.8.4.1 LFXT
        2. 6.8.4.2 HFXT
        3. 6.8.4.3 DCO
        4. 6.8.4.4 Very Low-Power Low-Frequency Oscillator (VLO)
        5. 6.8.4.5 Low-Frequency Reference Oscillator (REFO)
        6. 6.8.4.6 Module Oscillator (MODOSC)
        7. 6.8.4.7 System Oscillator (SYSOSC)
        8. 6.8.4.8 Fail-Safe Mechanisms
      5. 6.8.5 System Controller (SYSCTL)
    9. 6.9  Peripherals
      1. 6.9.1  Digital I/O
        1. 6.9.1.1 Glitch Filtering on Digital I/Os
      2. 6.9.2  Port Mapping Controller (PMAPCTL)
        1. 6.9.2.1 Port Mapping Definitions
      3. 6.9.3  Timer_A
        1. 6.9.3.1 Timer_A Signal Connection Tables
      4. 6.9.4  Timer32
      5. 6.9.5  Enhanced Universal Serial Communication Interface (eUSCI)
      6. 6.9.6  Real-Time Clock (RTC_C)
      7. 6.9.7  Watchdog Timer (WDT_A)
      8. 6.9.8  Precision ADC
      9. 6.9.9  Comparator_E (COMP_E)
      10. 6.9.10 Shared Reference (REF_A)
      11. 6.9.11 CRC32
      12. 6.9.12 AES256 Accelerator
      13. 6.9.13 True Random Seed
    10. 6.10 Code Development and Debug
      1. 6.10.1 JTAG and SWD Based Development, Debug, and Trace
      2. 6.10.2 Peripheral Halt Control
      3. 6.10.3 Bootloader (BSL)
      4. 6.10.4 Device Security
    11. 6.11 Performance Benchmarks
      1. 6.11.1 ULPBench Performance: 192.3 ULPMark-CP
      2. 6.11.2 CoreMark/MHz Performance: 3.41
      3. 6.11.3 DMIPS/MHz (Dhrystone 2.1) Performance: 1.22
    12. 6.12 Input/Output Diagrams
      1. 6.12.1  Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 6.12.2  Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger
      3. 6.12.3  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      4. 6.12.4  Port P9 (P9.4 to P9.7) Input/Output With Schmitt Trigger
      5. 6.12.5  Port P10 (P10.0 to P10.3) Input/Output With Schmitt Trigger
      6. 6.12.6  Port P2 (P2.4 to P2.7) Input/Output With Schmitt Trigger
      7. 6.12.7  Port P7 (P7.0 to P7.3) Input/Output With Schmitt Trigger
      8. 6.12.8  Port P9 (P9.2 and P9.3) Input/Output With Schmitt Trigger
      9. 6.12.9  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      10. 6.12.10 Port P5 (P5.0 to P5.5) Input/Output With Schmitt Trigger
      11. 6.12.11 Port P6 (P6.0 and P6.1) Input/Output With Schmitt Trigger
      12. 6.12.12 Port P8 (P8.2 to P8.7) Input/Output With Schmitt Trigger
      13. 6.12.13 Port P9 (P9.0 and P9.1) Input/Output With Schmitt Trigger
      14. 6.12.14 Port P5 (P5.6 and P5.7) Input/Output With Schmitt Trigger
      15. 6.12.15 Port P6 (P6.2 to P6.5) Input/Output With Schmitt Trigger
      16. 6.12.16 Port P6 (P6.6 and P6.7) Input/Output With Schmitt Trigger
      17. 6.12.17 Port P8 (P8.0 and P8.1) Input/Output With Schmitt Trigger
      18. 6.12.18 Port P10 (P10.4 and P10.5) Input/Output With Schmitt Trigger
      19. 6.12.19 Port P7 (P7.4 to P7.7) Input/Output With Schmitt Trigger
      20. 6.12.20 Port PJ (PJ.0 and PJ.1) Input/Output With Schmitt Trigger
      21. 6.12.21 Port PJ (PJ.2 and PJ.3) Input/Output With Schmitt Trigger
      22. 6.12.22 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
      23. 6.12.23 Ports SWCLKTCK and SWDIOTMS With Schmitt Trigger
    13. 6.13 Device Descriptors (TLV)
    14. 6.14 Identification
      1. 6.14.1 Revision Identification
      2. 6.14.2 Device Identification
      3. 6.14.3 Arm Cortex-M4F ROM Table Based Part Number
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 General Layout Recommendations
      4. 7.1.4 Do's and Don'ts
    2. 7.2 Peripheral and Interface-Specific Design Information
      1. 7.2.1 Precision ADC Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Layout Guidelines
  8. 8Device and Documentation Support
    1. 8.1  Getting Started and Next Steps
    2. 8.2  Device Nomenclature
    3. 8.3  Tools and Software
    4. 8.4  Documentation Support
    5. 8.5  Related Links
    6. 8.6  Community Resources
    7. 8.7  Trademarks
    8. 8.8  Electrostatic Discharge Caution
    9. 8.9  Export Control Notice
    10. 8.10 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PZ|100
  • ZXH|80
  • RGC|64
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pin Attributes

Table 4-1 describes the attributes of the pins.

Table 4-1 Pin Attributes

PIN NO.(7) SIGNAL NAME(1)(5) SIGNAL TYPE(2) BUFFER TYPE(3) POWER SOURCE(4) RESET STATE AFTER POR(6)
PZ ZXH RGC
1 N/A N/A P10.1 (RD) I/O LVCMOS DVCC OFF
UCB3CLK I/O LVCMOS DVCC N/A
2 N/A N/A P10.2 (RD) I/O LVCMOS DVCC OFF
UCB3SIMO I/O LVCMOS DVCC N/A
UCB3SDA I/O LVCMOS DVCC N/A
3 N/A N/A P10.3 (RD) I/O LVCMOS DVCC OFF
UCB3SOMI I/O LVCMOS DVCC N/A
UCB3SCL I/O LVCMOS DVCC N/A
4 A1 1 P1.0 (RD) I/O LVCMOS DVCC OFF
UCA0STE I/O LVCMOS DVCC N/A
5 B1 2 P1.1 (RD) I/O LVCMOS DVCC OFF
UCA0CLK I/O LVCMOS DVCC N/A
6 C4 3 P1.2 (RD) I/O LVCMOS DVCC OFF
UCA0RXD I LVCMOS DVCC N/A
UCA0SOMI I/O LVCMOS DVCC N/A
7 D4 4 P1.3 (RD) I/O LVCMOS DVCC OFF
UCA0TXD O LVCMOS DVCC N/A
UCA0SIMO I/O LVCMOS DVCC N/A
8 D3 5 P1.4 (RD) I/O LVCMOS DVCC OFF
UCB0STE I/O LVCMOS DVCC N/A
9 C1 6 P1.5 (RD) I/O LVCMOS DVCC OFF
UCB0CLK I/O LVCMOS DVCC N/A
10 D1 7 P1.6 (RD) I/O LVCMOS DVCC OFF
UCB0SIMO I/O LVCMOS DVCC N/A
UCB0SDA I/O LVCMOS DVCC N/A
11 E1 8 P1.7 (RD) I/O LVCMOS DVCC OFF
UCB0SOMI I/O LVCMOS DVCC N/A
UCB0SCL I/O LVCMOS DVCC N/A
12 C2 9 VCORE Power DVCC N/A
13 D2 10 DVCC1 Power N/A N/A
14 E2 11 VSW Power N/A N/A
15 F2 12 DVSS1 Power N/A N/A
16 E4 13 P2.0 (RD) I/O LVCMOS DVCC OFF
PM_UCA1STE I/O LVCMOS DVCC N/A
17 F1 14 P2.1 (RD) I/O LVCMOS DVCC OFF
PM_UCA1CLK I/O LVCMOS DVCC N/A
18 E3 15 P2.2 (RD) I/O LVCMOS DVCC OFF
PM_UCA1RXD I LVCMOS DVCC N/A
PM_UCA1SOMI I/O LVCMOS DVCC N/A
19 F4 16 P2.3 (RD) I/O LVCMOS DVCC OFF
PM_UCA1TXD O LVCMOS DVCC N/A
PM_UCA1SIMO I/O LVCMOS DVCC N/A
20 F3 N/A P2.4 (RD) I/O LVCMOS DVCC OFF
PM_TA0.1 I/O LVCMOS DVCC N/A
21 G1 N/A P2.5 (RD) I/O LVCMOS DVCC OFF
PM_TA0.2 I/O LVCMOS DVCC N/A
22 G2 N/A P2.6 (RD) I/O LVCMOS DVCC OFF
PM_TA0.3 I/O LVCMOS DVCC N/A
23 H1 N/A P2.7 (RD) I/O LVCMOS DVCC OFF
PM_TA0.4 I/O LVCMOS DVCC N/A
24 N/A N/A P10.4 (RD) I/O LVCMOS DVCC OFF
TA3.0 I/O LVCMOS DVCC N/A
C0.7 I Analog DVCC N/A
25 N/A N/A P10.5 (RD) I/O LVCMOS DVCC OFF
TA3.1 I/O LVCMOS DVCC N/A
C0.6 I Analog DVCC N/A
26 J1 N/A P7.4 (RD) I/O LVCMOS DVCC OFF
PM_TA1.4 I/O LVCMOS DVCC N/A
C0.5 I Analog DVCC N/A
27 H2 N/A P7.5 (RD) I/O LVCMOS DVCC OFF
PM_TA1.3 I/O LVCMOS DVCC N/A
C0.4 I Analog DVCC N/A
28 J2 N/A P7.6 (RD) I/O LVCMOS DVCC OFF
PM_TA1.2 I/O LVCMOS DVCC N/A
C0.3 I Analog DVCC N/A
29 G3 N/A P7.7 (RD) I/O LVCMOS DVCC OFF
PM_TA1.1 I/O LVCMOS DVCC N/A
C0.2 I Analog DVCC N/A
30 H3 17 P8.0 (RD) I/O LVCMOS DVCC OFF
UCB3STE I/O LVCMOS DVCC N/A
TA1.0 I/O LVCMOS DVCC N/A
C0.1 I Analog DVCC N/A
31 G4 18 P8.1 (RD) I/O LVCMOS DVCC OFF
UCB3CLK I/O LVCMOS DVCC N/A
TA2.0 I/O LVCMOS DVCC N/A
C0.0 I Analog DVCC N/A
32 J3 19 P3.0 (RD) I/O LVCMOS DVCC OFF
PM_UCA2STE I/O LVCMOS DVCC N/A
33 H4 20 P3.1 (RD) I/O LVCMOS DVCC OFF
PM_UCA2CLK I/O LVCMOS DVCC N/A
34 G5 21 P3.2 (RD) I/O LVCMOS DVCC OFF
PM_UCA2RXD I LVCMOS DVCC N/A
PM_UCA2SOMI I/O LVCMOS DVCC N/A
35 J4 22 P3.3 (RD) I/O LVCMOS DVCC OFF
PM_UCA2TXD O LVCMOS DVCC N/A
PM_UCA2SIMO I/O LVCMOS DVCC N/A
36 H5 23 P3.4 (RD) I/O LVCMOS DVCC OFF
PM_UCB2STE I/O LVCMOS DVCC N/A
37 G6 24 P3.5 (RD) I/O LVCMOS DVCC OFF
PM_UCB2CLK I/O LVCMOS DVCC N/A
38 J5 25 P3.6 (RD) I/O LVCMOS DVCC OFF
PM_UCB2SIMO I/O LVCMOS DVCC N/A
PM_UCB2SDA I/O LVCMOS DVCC N/A
39 H6 26 P3.7 (RD) I/O LVCMOS DVCC OFF
PM_UCB2SOMI I/O LVCMOS DVCC N/A
PM_UCB2SCL I LVCMOS DVCC N/A
40 E5 27 AVSS3 Power N/A N/A
41 J6 28 PJ.0 (RD) I/O LVCMOS DVCC OFF
LFXIN I Analog DVCC N/A
42 J7 29 PJ.1 (RD) I/O LVCMOS DVCC OFF
LFXOUT O Analog DVCC N/A
43 F5 30 AVSS1 Power N/A N/A
44 J8 31 DCOR Analog N/A N/A
45 F6 32 AVCC1 Power N/A N/A
46 N/A N/A P8.2 (RD) I/O LVCMOS DVCC OFF
TA3.2 I/O LVCMOS DVCC N/A
A23 I Analog DVCC N/A
47 N/A N/A P8.3 (RD) I/O LVCMOS DVCC OFF
TA3CLK I LVCMOS DVCC N/A
A22 I Analog DVCC N/A
48 N/A N/A P8.4 (RD) I/O LVCMOS DVCC OFF
A21 I Analog DVCC N/A
49 N/A N/A P8.5 (RD) I/O LVCMOS DVCC OFF
A20 I Analog DVCC N/A
50 N/A N/A P8.6 (RD) I/O LVCMOS DVCC OFF
A19 I Analog DVCC N/A
51 N/A N/A P8.7 (RD) I/O LVCMOS DVCC OFF
A18 I Analog DVCC N/A
52 N/A N/A P9.0 (RD) I/O LVCMOS DVCC OFF
A17 I Analog DVCC N/A
53 N/A N/A P9.1 (RD) I/O LVCMOS DVCC OFF
A16 I Analog DVCC N/A
54 J9 N/A P6.0 (RD) I/O LVCMOS DVCC OFF
A15 I Analog DVCC N/A
55 H7 N/A P6.1 (RD) I/O LVCMOS DVCC OFF
A14 I Analog DVCC N/A
56 H9 N/A P4.0 (RD) I/O LVCMOS DVCC OFF
A13 I Analog DVCC N/A
57 H8 N/A P4.1 (RD) I/O LVCMOS DVCC OFF
A12 I Analog DVCC N/A
58 G7 33 P4.2 (RD) I/O LVCMOS DVCC OFF
ACLK O LVCMOS DVCC N/A
TA2CLK I LVCMOS DVCC N/A
A11 I Analog DVCC N/A
59 G8 34 P4.3 (RD) I/O LVCMOS DVCC OFF
MCLK O LVCMOS DVCC N/A
RTCCLK O LVCMOS DVCC N/A
A10 I Analog DVCC N/A
60 G9 35 P4.4 (RD) I/O LVCMOS DVCC OFF
HSMCLK O LVCMOS DVCC N/A
SVMHOUT O LVCMOS DVCC N/A
A9 I Analog DVCC N/A
61 F7 36 P4.5 (RD) I/O LVCMOS DVCC OFF
A8 I Analog DVCC N/A
62 F8 37 P4.6 (RD) I/O LVCMOS DVCC OFF
A7 I Analog DVCC N/A
63 F9 38 P4.7 (RD) I/O LVCMOS DVCC OFF
A6 I Analog DVCC N/A
64 E7 39 P5.0 (RD) I/O LVCMOS DVCC OFF
A5 I Analog DVCC N/A
65 E8 40 P5.1 (RD) I/O LVCMOS DVCC OFF
A4 I Analog DVCC N/A
66 E9 41 P5.2 (RD) I/O LVCMOS DVCC OFF
A3 I Analog DVCC N/A
67 D7 42 P5.3 (RD) I/O LVCMOS DVCC OFF
A2 I Analog DVCC N/A
68 D8 43 P5.4 (RD) I/O LVCMOS DVCC OFF
A1 I Analog DVCC N/A
69 C8 44 P5.5 (RD) I/O LVCMOS DVCC OFF
A0 I Analog DVCC N/A
70 D9 45 P5.6 (RD) I/O LVCMOS DVCC OFF
TA2.1 I/O LVCMOS DVCC N/A
VREF+ O Analog DVCC N/A
VeREF+ I Analog DVCC N/A
C1.7 I Analog DVCC N/A
71 C9 46 P5.7 (RD) I/O LVCMOS DVCC OFF
TA2.2 I/O LVCMOS DVCC N/A
VREF- O Analog DVCC N/A
VeREF- I Analog DVCC N/A
C1.6 I Analog DVCC N/A
72 E6 47 DVSS2 Power N/A N/A
73 C6 48 DVCC2 Power N/A N/A
74 N/A N/A P9.2 (RD) I/O LVCMOS DVCC OFF
TA3.3 I/O LVCMOS DVCC N/A
75 N/A N/A P9.3 (RD) I/O LVCMOS DVCC OFF
TA3.4 I/O LVCMOS DVCC N/A
76 A9 N/A P6.2 (RD) I/O LVCMOS DVCC OFF
UCB1STE I/O LVCMOS DVCC N/A
C1.5 I Analog DVCC N/A
77 B9 N/A P6.3 (RD) I/O LVCMOS DVCC OFF
UCB1CLK I/O LVCMOS DVCC N/A
C1.4 I Analog DVCC N/A
78 A8 N/A P6.4 (RD) I/O LVCMOS DVCC OFF
UCB1SIMO I/O LVCMOS DVCC N/A
UCB1SDA I/O LVCMOS DVCC N/A
C1.3 I Analog DVCC N/A
79 A7 N/A P6.5 (RD) I/O LVCMOS DVCC OFF
UCB1SOMI I/O LVCMOS DVCC N/A
UCB1SCL I/O LVCMOS DVCC N/A
C1.2 I Analog DVCC N/A
80 B8 49 P6.6 (RD) I/O LVCMOS DVCC OFF
TA2.3 I/O LVCMOS DVCC N/A
UCB3SIMO I/O LVCMOS DVCC N/A
UCB3SDA I/O LVCMOS DVCC N/A
C1.1 I Analog DVCC N/A
81 B7 50 P6.7 (RD) I/O LVCMOS DVCC OFF
TA2.4 I/O LVCMOS DVCC N/A
UCB3SOMI I/O LVCMOS DVCC N/A
UCB3SCL I/O LVCMOS DVCC N/A
C1.0 I Analog DVCC N/A
82 C7 51 DVSS3 Power N/A N/A
83 B6 52 RSTn (RD) I LVCMOS DVCC PU
NMI I LVCMOS DVCC N/A
84 D6 53 AVSS2 Power N/A N/A
85 A6 54 PJ.2 (RD) I/O LVCMOS DVCC OFF
HFXOUT O Analog DVCC N/A
86 A5 55 PJ.3 (RD) I/O LVCMOS DVCC OFF
HFXIN I Analog DVCC N/A
87 D5 56 AVCC2 Power N/A N/A
88 B5 57 P7.0 (RD) I/O LVCMOS DVCC OFF
PM_SMCLK O LVCMOS DVCC N/A
PM_DMAE0 I LVCMOS DVCC N/A
89 C5 58 P7.1 (RD) I/O LVCMOS DVCC OFF
PM_C0OUT O LVCMOS DVCC N/A
PM_TA0CLK I LVCMOS DVCC N/A
90 B4 59 P7.2 (RD) I/O LVCMOS DVCC OFF
PM_C1OUT O LVCMOS DVCC N/A
PM_TA1CLK I LVCMOS DVCC N/A
91 A4 60 P7.3 (RD) I/O LVCMOS DVCC OFF
PM_TA0.0 I/O LVCMOS DVCC N/A
92 B3 61 PJ.4 I/O LVCMOS DVCC N/A
TDI (RD) I LVCMOS DVCC PU
93 A3 62 PJ.5 I/O LVCMOS DVCC N/A
TDO (RD) O LVCMOS DVCC N/A
SWO O LVCMOS DVCC N/A
94 B2 63 SWDIOTMS I/O LVCMOS DVCC PU
95 A2 64 SWCLKTCK I LVCMOS DVCC PD
96 N/A N/A P9.4 (RD) I/O LVCMOS DVCC OFF
UCA3STE I/O LVCMOS DVCC N/A
97 N/A N/A P9.5 (RD) I/O LVCMOS DVCC OFF
UCA3CLK I/O LVCMOS DVCC N/A
98 N/A N/A P9.6 (RD) I/O LVCMOS DVCC OFF
UCA3RXD I LVCMOS DVCC N/A
UCA3SOMI I/O LVCMOS DVCC N/A
99 N/A N/A P9.7 (RD) I/O LVCMOS DVCC OFF
UCA3TXD O LVCMOS DVCC N/A
UCA3SIMO I/O LVCMOS DVCC N/A
100 N/A N/A P10.0 (RD) I/O LVCMOS DVCC OFF
UCB3STE I/O LVCMOS DVCC N/A
N/A N/A Pad QFN Pad N/A
(RD) indicates the reset default signal name for that pin.
Signal Types: I = Input, O = Output, I/O = Input or Output, P = power
Buffer Types: see Table 4-3 for details
The power source shown in this table is the I/O power source, which may differ from the module power source.
To determine the pin mux encodings for each pin, see Section 6.12.
Reset States:
OFF = High-impedance with Schmitt trigger and pullup or pulldown (if available) disabled
PD = High-impedance input with pulldown enabled
PU = High-impedance input with pullup enabled
N/A = Not applicable
N/A = not available on this package