SLAS826H March 2015 – June 2019 MSP432P401M , MSP432P401R
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
The port mapping controller on MSP432P401x MCUs allows reconfigurable mapping of digital functions on ports P2, P3, and P7. Table 6-44 lists the available mappings. Table 6-45 lists the default settings for all pins that support port mapping.
VALUE | PxMAPy MNEMONIC | INPUT PIN FUNCTION | OUTPUT PIN FUNCTION |
---|---|---|---|
0 | PM_NONE | None | DVSS |
1 | PM_UCA0CLK | eUSCI_A0 clock input/output (direction controlled by eUSCI) | |
2 | PM_UCA0RXD | eUSCI_A0 UART RXD (direction controlled by eUSCI – Input) | |
PM_UCA0SOMI | eUSCI_A0 SPI slave out master in (direction controlled by eUSCI) | ||
3 | PM_UCA0TXD | eUSCI_A0 UART TXD (direction controlled by eUSCI – Output) | |
PM_UCA0SIMO | eUSCI_A0 SPI slave in master out (direction controlled by eUSCI) | ||
4 | PM_UCB0CLK | eUSCI_B0 clock input/output (direction controlled by eUSCI) | |
5 | PM_UCB0SDA | eUSCI_B0 I2C data (open drain and direction controlled by eUSCI) | |
PM_UCB0SIMO | eUSCI_B0 SPI slave in master out (direction controlled by eUSCI) | ||
6 | PM_UCB0SCL | eUSCI_B0 I2C clock (open drain and direction controlled by eUSCI) | |
PM_UCB0SOMI | eUSCI_B0 SPI slave out master in (direction controlled by eUSCI) | ||
7 | PM_UCA1STE | eUSCI_A1 SPI slave transmit enable (direction controlled by eUSCI) | |
8 | PM_UCA1CLK | eUSCI_A1 clock input/output (direction controlled by eUSCI) | |
9 | PM_UCA1RXD | eUSCI_A1 UART RXD (direction controlled by eUSCI – Input) | |
PM_UCA1SOMI | eUSCI_A1 SPI slave out master in (direction controlled by eUSCI) | ||
10 | PM_UCA1TXD | eUSCI_A1 UART TXD (direction controlled by eUSCI – Output) | |
PM_UCA1SIMO | eUSCI_A1 SPI slave in master out (direction controlled by eUSCI) | ||
11 | PM_UCA2STE | eUSCI_A2 SPI slave transmit enable (direction controlled by eUSCI) | |
12 | PM_UCA2CLK | eUSCI_A2 clock input/output (direction controlled by eUSCI) | |
13 | PM_UCA2RXD | eUSCI_A2 UART RXD (direction controlled by eUSCI – Input) | |
PM_UCA2SOMI | eUSCI_A2 SPI slave out master in (direction controlled by eUSCI) | ||
14 | PM_UCA2TXD | eUSCI_A2 UART TXD (direction controlled by eUSCI – Output) | |
PM_ UCA2SIMO | eUSCI_A2 SPI slave in master out (direction controlled by eUSCI) | ||
15 | PM_UCB2STE | eUSCI_B2 SPI slave transmit enable (direction controlled by eUSCI) | |
16 | PM_UCB2CLK | eUSCI_B2 clock input/output (direction controlled by eUSCI) | |
17 | PM_UCB2SDA | eUSCI_B2 I2C data (open drain and direction controlled by eUSCI) | |
PM_UCB2SIMO | eUSCI_B2 SPI slave in master out (direction controlled by eUSCI) | ||
18 | PM_UCB2SCL | eUSCI_B2 I2C clock (open drain and direction controlled by eUSCI) | |
PM_UCB2SOMI | eUSCI_B2 SPI slave out master in (direction controlled by eUSCI) | ||
19 | PM_TA0CCR0A | TA0 CCR0 capture input CCI0A | TA0 CCR0 compare output Out0 |
20 | PM_TA0CCR1A | TA0 CCR1 capture input CCI1A | TA0 CCR1 compare output Out1 |
21 | PM_TA0CCR2A | TA0 CCR2 capture input CCI2A | TA0 CCR2 compare output Out2 |
22 | PM_TA0CCR3A | TA0 CCR3 capture input CCI3A | TA0 CCR3 compare output Out3 |
23 | PM_TA0CCR4A | TA0 CCR4 capture input CCI4A | TA0 CCR4 compare output Out4 |
24 | PM_TA1CCR1A | TA1 CCR1 capture input CCI1A | TA1 CCR1 compare output Out1 |
25 | PM_TA1CCR2A | TA1 CCR2 capture input CCI2A | TA1 CCR2 compare output Out2 |
26 | PM_TA1CCR3A | TA1 CCR3 capture input CCI3A | TA1 CCR3 compare output Out3 |
27 | PM_TA1CCR4A | TA1 CCR4 capture input CCI4A | TA1 CCR4 compare output Out4 |
28 | PM_TA0CLK | Timer_A0 external clock input | None |
PM_C0OUT | None | Comparator-E0 output | |
29 | PM_TA1CLK | Timer_A1 external clock input | None |
PM_C1OUT | None | Comparator-E1 output | |
30 | PM_DMAE0 | DMAE0 input | None |
PM_SMCLK | None | SMCLK | |
31 (0FFh)(1) | PM_ANALOG | Disables the output driver and the input Schmitt-trigger to prevent parasitic cross currents when applying analog signals. |
PIN NAME | PxMAPy MNEMONIC | INPUT PIN FUNCTION | OUTPUT PIN FUNCTION |
---|---|---|---|
P2.0/PM_UCA1STE | PM_UCA1STE | eUSCI_A1 SPI slave transmit enable (direction controlled by eUSCI) | |
P2.1/PM_UCA1CLK | PM_UCA1CLK | eUSCI_A1 clock input/output (direction controlled by eUSCI) | |
P2.2/PM_UCA1RXD/ PM_UCA1SOMI | PM_UCA1RXD/
PM_UCA1SOMI |
eUSCI_A1 UART RXD (direction controlled by eUSCI – input)
eUSCI_A1 SPI slave out master in (direction controlled by eUSCI) |
|
P2.3/PM_UCA1TXD/ PM_UCA1SIMO | PM_UCA1TXD/
PM_UCA1SIMO |
eUSCI_A1 UART TXD (direction controlled by eUSCI – output)/
eUSCI_A1 SPI slave in master out (direction controlled by eUSCI) |
|
P2.4/PM_TA0.1(1) | PM_TA0CCR1A | TA0 CCR1 capture input CCI1A | TA0 CCR1 compare output Out1 |
P2.5/PM_TA0.2(1) | PM_TA0CCR2A | TA0 CCR2 capture input CCI2A | TA0 CCR2 compare output Out2 |
P2.6/PM_TA0.3(1) | PM_TA0CCR3A | TA0 CCR3 capture input CCI3A | TA0 CCR3 compare output Out3 |
P2.7/PM_TA0.4(1) | PM_TA0CCR4A | TA0 CCR4 capture input CCI4A | TA0 CCR4 compare output Out4 |
P3.0/PM_UCA2STE | PM_UCA2STE | eUSCI_A2 SPI slave transmit enable (direction controlled by eUSCI) | |
P3.1/PM_UCA2CLK | PM_UCA2CLK | eUSCI_A2 clock input/output (direction controlled by eUSCI) | |
P3.2/PM_UCA2RXD/ PM_UCA2SOMI | PM_UCA2RXD/
PM_UCA2SOMI |
eUSCI_A2 UART RXD (direction controlled by eUSCI – input)/
eUSCI_A2 SPI slave out master in (direction controlled by eUSCI) |
|
P3.3/PM_UCA2TXD/ PM_UCA2SIMO | PM_UCA2TXD/
PM_UCA2SIMO |
eUSCI_A2 UART TXD (direction controlled by eUSCI – output)/
eUSCI_A2 SPI slave in master out (direction controlled by eUSCI) |
|
P3.4/PM_UCB2STE | PM_UCB2STE | eUSCI_B2 SPI slave transmit enable (direction controlled by eUSCI) | |
P3.5/PM_UCB2CLK | PM_UCB2CLK | eUSCI_B2 clock input/output (direction controlled by eUSCI) | |
P3.6/PM_UCB2SIMO/ PM_UCB2SDA | PM_UCB2SIMO/
PM_UCB2SDA |
eUSCI_B2 SPI slave in master out (direction controlled by eUSCI)/
eUSCI_B2 I2C data (open drain and direction controlled by eUSCI) |
|
P3.7/PM_UCB2SOMI/ PM_UCB2SCL | PM_UCB2SOMI/
PM_UCB2SCL |
eUSCI_B2 SPI slave out master in (direction controlled by eUSCI)/
eUSCI_B2 I2C clock (open drain and direction controlled by eUSCI) |
|
P7.0/PM_SMCLK/ PM_DMAE0 | PM_SMCLK/
PM_DMAE0 |
DMAE0 input | SMCLK |
P7.1/PM_C0OUT/ PM_TA0CLK | PM_C0OUT/
PM_TA0CLK |
Timer_A0 external clock input | Comparator-E0 output |
P7.2/PM_C1OUT/ PM_TA1CLK | PM_C1OUT/
PM_TA1CLK |
Timer_A1 external clock input | Comparator-E1 output |
P7.3/PM_TA0.0 | PM_TA0CCR0A | TA0 CCR0 capture input CCI0A | TA0 CCR0 compare output Out0 |
P7.4/PM_TA1.4/C0.5(1) | PM_TA1CCR4A | TA1 CCR4 capture input CCI4A | TA1 CCR4 compare output Out4 |
P7.5/PM_TA1.3/C0.4(1) | PM_TA1CCR3A | TA1 CCR3 capture input CCI3A | TA1 CCR3 compare output Out3 |
P7.6/PM_TA1.2/C0.3(1) | PM_TA1CCR2A | TA1 CCR2 capture input CCI2A | TA1 CCR2 compare output Out2 |
P7.7/PM_TA1.1/C0.2(1) | PM_TA1CCR1A | TA1 CCR1 capture input CCI1A | TA1 CCR1 compare output Out1 |