SLAS826H March   2015  – June 2019 MSP432P401M , MSP432P401R

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. Table 4-2 Signal Descriptions
    4. 4.4 Pin Multiplexing
    5. 4.5 Buffer Types
    6. 4.6 Connection for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Recommended External Components
    5. 5.5  Operating Mode VCC Ranges
    6. 5.6  Operating Mode CPU Frequency Ranges
    7. 5.7  Operating Mode Peripheral Frequency Ranges
    8. 5.8  Operating Mode Execution Frequency vs Flash Wait-State Requirements
    9. 5.9  Current Consumption During Device Reset of the 100-pin LQFP Package
    10. 5.10 Current Consumption in LDO-Based Active Modes – Dhrystone 2.1 Program
    11. 5.11 Current Consumption in DC-DC-Based Active Modes – Dhrystone 2.1 Program
    12. 5.12 Current Consumption in Low-Frequency Active Modes – Dhrystone 2.1 Program
    13. 5.13 Typical Characteristics of Active Mode Currents for CoreMark Program
    14. 5.14 Typical Characteristics of Active Mode Currents for Prime Number Program
    15. 5.15 Typical Characteristics of Active Mode Currents for Fibonacci Program
    16. 5.16 Typical Characteristics of Active Mode Currents for While(1) Program
    17. 5.17 Typical Characteristics of Low-Frequency Active Mode Currents for CoreMark Program
    18. 5.18 Current Consumption in LDO-Based LPM0 Modes
    19. 5.19 Current Consumption in DC-DC-Based LPM0 Modes
    20. 5.20 Current Consumption in Low-Frequency LPM0 Modes
    21. 5.21 Current Consumption in LPM3, LPM4 Modes
    22. 5.22 Current Consumption in LPM3.5, LPM4.5 Modes
    23. 5.23 Current Consumption of Digital Peripherals
    24. 5.24 Thermal Resistance Characteristics
    25. 5.25 Timing and Switching Characteristics
      1. 5.25.1  Reset Timing
        1. Table 5-1 Reset Recovery Latencies
        2. Table 5-2 External Reset Recovery Latencies
      2. 5.25.2  Peripheral Register Access Timing
        1. Table 5-3 Peripheral Register Access Latency
      3. 5.25.3  Mode Transition Timing
        1. Table 5-4 Active Mode Transition Latencies
        2. Table 5-5 LPM0 Mode Transition Latencies
        3. Table 5-6 LPM3, LPM4 Mode Transition Latencies
        4. Table 5-7 LPM3.5, LPM4.5 Mode Transition Latencies
      4. 5.25.4  Clock Specifications
        1. Table 5-8  Low-Frequency Crystal Oscillator, LFXT, Recommended Operating Conditions
        2. Table 5-9  Low-Frequency Crystal Oscillator, LFXT
        3. Table 5-10 High-Frequency Crystal Oscillator, HFXT, Recommended Operating Conditions
        4. Table 5-11 High-Frequency Crystal Oscillator, HFXT
        5. Table 5-12 DCO
        6. Table 5-13 DCO Overall Tolerance
        7. Table 5-14 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        8. Table 5-15 Internal-Reference Low-Frequency Oscillator (REFO) in 32.768-kHz Mode
        9. Table 5-16 Internal-Reference Low-Frequency Oscillator (REFO) in 128-kHz Mode
        10. Table 5-17 Module Oscillator (MODOSC)
        11. Table 5-18 System Oscillator (SYSOSC)
      5. 5.25.5  Power Supply System
        1. Table 5-19 VCORE Regulator (LDO) Characteristics
        2. Table 5-20 VCORE Regulator (DC-DC) Characteristics
        3. Table 5-21 PSS, VCCDET
        4. Table 5-22 PSS, SVSMH
      6. 5.25.6  Digital I/Os
        1. Table 5-23 Digital Inputs (Applies to Both Normal and High-Drive I/Os)
        2. Table 5-24 Digital Outputs, Normal I/Os
        3. Table 5-25 Digital Outputs, High-Drive I/Os
        4. Table 5-26 Pin-Oscillator Frequency, Ports Px
        5. 5.25.6.1   Typical Characteristics, Normal-Drive I/O Outputs at 3.0 V and 2.2 V
        6. 5.25.6.2   Typical Characteristics, High-Drive I/O Outputs at 3.0 V and 2.2 V
        7. 5.25.6.3   Typical Characteristics, Pin-Oscillator Frequency
      7. 5.25.7  Precision ADC
        1. Table 5-27 Precision ADC, Power Supply and Input Range Conditions
        2. Table 5-28 Precision ADC, Timing Parameters
        3. Table 5-29 Precision ADC, Linearity Parameters
        4. Table 5-30 Precision ADC, Dynamic Parameters
        5. Table 5-31 Precision ADC, Temperature Sensor and Built-In V1/2
        6. Table 5-32 Precision ADC, Internal Reference Buffers
        7. Table 5-33 Precision ADC, External Reference
        8. 5.25.7.1   Typical Characteristics of ADC
      8. 5.25.8  REF_A
        1. Table 5-34 REF_A, Built-In Reference (LDO Operation)
      9. 5.25.9  Comparator_E
        1. Table 5-35 Comparator_E
      10. 5.25.10 eUSCI
        1. Table 5-36 eUSCI Clock Frequency (UART Mode)
        2. Table 5-37 eUSCI Switching Characteristics (UART Mode)
        3. Table 5-38 eUSCI Clock Frequency (SPI Master Mode)
        4. Table 5-39 eUSCI Switching Characteristics (SPI Master Mode)
        5. Table 5-40 eUSCI Switching Characteristics (SPI Slave Mode)
        6. Table 5-41 eUSCI Clock Frequency (I2C Mode)
        7. Table 5-42 eUSCI Switching Characteristics (I2C Mode)
      11. 5.25.11 Timers
        1. Table 5-43 Timer_A
        2. Table 5-44 Timer32
      12. 5.25.12 Memories
        1. Table 5-45 Flash Memory
        2. Table 5-46 Flash Operations Using MSP432 Peripheral Driver Libraries
        3. Table 5-47 Flash Stand-Alone Operations
        4. Table 5-48 SRAM
      13. 5.25.13 Emulation and Debug
        1. Table 5-49 JTAG
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  Processor and Execution Features
      1. 6.2.1 Floating-Point Unit
      2. 6.2.2 Memory Protection Unit
      3. 6.2.3 Nested Vectored Interrupt Controller (NVIC)
      4. 6.2.4 SysTick
      5. 6.2.5 Debug and Trace Features
    3. 6.3  Memory Map
      1. 6.3.1 Code Zone Memory Map
        1. 6.3.1.1 Flash Memory Region
        2. 6.3.1.2 SRAM Region
        3. 6.3.1.3 ROM Region
      2. 6.3.2 SRAM Zone Memory Map
        1. 6.3.2.1 SRAM Region
        2. 6.3.2.2 SRAM Bit-Band Alias Region
      3. 6.3.3 Peripheral Zone Memory Map
        1. 6.3.3.1 Peripheral Region
        2. 6.3.3.2 Peripheral Bit Band Alias Region
      4. 6.3.4 Debug and Trace Peripheral Zone
    4. 6.4  Memories on the MSP432P401x
      1. 6.4.1 Flash Memory
        1. 6.4.1.1 Flash Main Memory (0x0000_0000 to 0x0003_FFFF)
        2. 6.4.1.2 Flash Information Memory (0x0020_0000 to 0x0020_3FFF)
        3. 6.4.1.3 Flash Operation
      2. 6.4.2 SRAM
        1. 6.4.2.1 SRAM Bank Enable Configuration
        2. 6.4.2.2 SRAM Bank Retention Configuration and Backup Memory
      3. 6.4.3 ROM
    5. 6.5  DMA
      1. 6.5.1 DMA Source Mapping
      2. 6.5.2 DMA Completion Interrupts
      3. 6.5.3 DMA Access Privileges
    6. 6.6  Memory Map Access Details
      1. 6.6.1 Master and Slave Access Priority Settings
      2. 6.6.2 Memory Map Access Response
    7. 6.7  Interrupts
      1. 6.7.1 NMI
      2. 6.7.2 Device-Level User Interrupts
    8. 6.8  System Control
      1. 6.8.1 Device Resets
        1. 6.8.1.1 Power On/Off Reset (POR)
        2. 6.8.1.2 Reboot Reset
        3. 6.8.1.3 Hard Reset
        4. 6.8.1.4 Soft Reset
      2. 6.8.2 Power Supply System (PSS)
        1. 6.8.2.1 VCCDET
        2. 6.8.2.2 Supply Supervisor and Monitor for High Side (SVSMH)
        3. 6.8.2.3 Core Voltage Regulator
      3. 6.8.3 Power Control Manager (PCM)
      4. 6.8.4 Clock System (CS)
        1. 6.8.4.1 LFXT
        2. 6.8.4.2 HFXT
        3. 6.8.4.3 DCO
        4. 6.8.4.4 Very Low-Power Low-Frequency Oscillator (VLO)
        5. 6.8.4.5 Low-Frequency Reference Oscillator (REFO)
        6. 6.8.4.6 Module Oscillator (MODOSC)
        7. 6.8.4.7 System Oscillator (SYSOSC)
        8. 6.8.4.8 Fail-Safe Mechanisms
      5. 6.8.5 System Controller (SYSCTL)
    9. 6.9  Peripherals
      1. 6.9.1  Digital I/O
        1. 6.9.1.1 Glitch Filtering on Digital I/Os
      2. 6.9.2  Port Mapping Controller (PMAPCTL)
        1. 6.9.2.1 Port Mapping Definitions
      3. 6.9.3  Timer_A
        1. 6.9.3.1 Timer_A Signal Connection Tables
      4. 6.9.4  Timer32
      5. 6.9.5  Enhanced Universal Serial Communication Interface (eUSCI)
      6. 6.9.6  Real-Time Clock (RTC_C)
      7. 6.9.7  Watchdog Timer (WDT_A)
      8. 6.9.8  Precision ADC
      9. 6.9.9  Comparator_E (COMP_E)
      10. 6.9.10 Shared Reference (REF_A)
      11. 6.9.11 CRC32
      12. 6.9.12 AES256 Accelerator
      13. 6.9.13 True Random Seed
    10. 6.10 Code Development and Debug
      1. 6.10.1 JTAG and SWD Based Development, Debug, and Trace
      2. 6.10.2 Peripheral Halt Control
      3. 6.10.3 Bootloader (BSL)
      4. 6.10.4 Device Security
    11. 6.11 Performance Benchmarks
      1. 6.11.1 ULPBench Performance: 192.3 ULPMark-CP
      2. 6.11.2 CoreMark/MHz Performance: 3.41
      3. 6.11.3 DMIPS/MHz (Dhrystone 2.1) Performance: 1.22
    12. 6.12 Input/Output Diagrams
      1. 6.12.1  Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 6.12.2  Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger
      3. 6.12.3  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      4. 6.12.4  Port P9 (P9.4 to P9.7) Input/Output With Schmitt Trigger
      5. 6.12.5  Port P10 (P10.0 to P10.3) Input/Output With Schmitt Trigger
      6. 6.12.6  Port P2 (P2.4 to P2.7) Input/Output With Schmitt Trigger
      7. 6.12.7  Port P7 (P7.0 to P7.3) Input/Output With Schmitt Trigger
      8. 6.12.8  Port P9 (P9.2 and P9.3) Input/Output With Schmitt Trigger
      9. 6.12.9  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      10. 6.12.10 Port P5 (P5.0 to P5.5) Input/Output With Schmitt Trigger
      11. 6.12.11 Port P6 (P6.0 and P6.1) Input/Output With Schmitt Trigger
      12. 6.12.12 Port P8 (P8.2 to P8.7) Input/Output With Schmitt Trigger
      13. 6.12.13 Port P9 (P9.0 and P9.1) Input/Output With Schmitt Trigger
      14. 6.12.14 Port P5 (P5.6 and P5.7) Input/Output With Schmitt Trigger
      15. 6.12.15 Port P6 (P6.2 to P6.5) Input/Output With Schmitt Trigger
      16. 6.12.16 Port P6 (P6.6 and P6.7) Input/Output With Schmitt Trigger
      17. 6.12.17 Port P8 (P8.0 and P8.1) Input/Output With Schmitt Trigger
      18. 6.12.18 Port P10 (P10.4 and P10.5) Input/Output With Schmitt Trigger
      19. 6.12.19 Port P7 (P7.4 to P7.7) Input/Output With Schmitt Trigger
      20. 6.12.20 Port PJ (PJ.0 and PJ.1) Input/Output With Schmitt Trigger
      21. 6.12.21 Port PJ (PJ.2 and PJ.3) Input/Output With Schmitt Trigger
      22. 6.12.22 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
      23. 6.12.23 Ports SWCLKTCK and SWDIOTMS With Schmitt Trigger
    13. 6.13 Device Descriptors (TLV)
    14. 6.14 Identification
      1. 6.14.1 Revision Identification
      2. 6.14.2 Device Identification
      3. 6.14.3 Arm Cortex-M4F ROM Table Based Part Number
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 General Layout Recommendations
      4. 7.1.4 Do's and Don'ts
    2. 7.2 Peripheral and Interface-Specific Design Information
      1. 7.2.1 Precision ADC Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Layout Guidelines
  8. 8Device and Documentation Support
    1. 8.1  Getting Started and Next Steps
    2. 8.2  Device Nomenclature
    3. 8.3  Tools and Software
    4. 8.4  Documentation Support
    5. 8.5  Related Links
    6. 8.6  Community Resources
    7. 8.7  Trademarks
    8. 8.8  Electrostatic Discharge Caution
    9. 8.9  Export Control Notice
    10. 8.10 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PZ|100
  • ZXH|80
  • RGC|64
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Signal Descriptions

Table 4-2 describes the signals for all device variants and package options.

Table 4-2 Signal Descriptions

FUNCTION SIGNAL NAME SIGNAL NO.(2) SIGNAL TYPE(1) DESCRIPTION
PZ ZXH RGC
ADC A0 69 C8 44 I ADC analog input A0
A1 68 D8 43 I ADC analog input A1
A2 67 D7 42 I ADC analog input A2
A3 66 E9 41 I ADC analog input A3
A4 65 E8 40 I ADC analog input A4
A5 64 E7 39 I ADC analog input A5
A6 63 F9 38 I ADC analog input A6
A7 62 F8 37 I ADC analog input A7
A8 61 F7 36 I ADC analog input A8
A9 60 G9 35 I ADC analog input A9
A10 59 G8 34 I ADC analog input A10
A11 58 G7 33 I ADC analog input A11
A12 57 H8 N/A I ADC analog input A12
A13 56 H9 N/A I ADC analog input A13
A14 55 H7 N/A I ADC analog input A14
A15 54 J9 N/A I ADC analog input A15
A16 53 N/A N/A I ADC analog input A16
A17 52 N/A N/A I ADC analog input A17
A18 51 N/A N/A I ADC analog input A18
A19 50 N/A N/A I ADC analog input A19
A20 49 N/A N/A I ADC analog input A20
A21 48 N/A N/A I ADC analog input A21
A22 47 N/A N/A I ADC analog input A22
A23 46 N/A N/A I ADC analog input A23
Clock ACLK 58 G7 33 O ACLK clock output
DCOR 44 J8 31 DCO external resistor pin
HFXIN 86 A5 55 I Input for high-frequency crystal oscillator HFXT
HFXOUT 85 A6 54 O Output for high-frequency crystal oscillator HFXT
HSMCLK 60 G9 35 O HSMCLK clock output
LFXIN 41 J6 28 I Input for low-frequency crystal oscillator LFXT
LFXOUT 42 J7 29 O Output of low-frequency crystal oscillator LFXT
MCLK 59 G8 34 O MCLK clock output
Comparator C0.0 31 G4 18 I Comparator_E0 input 0
C0.1 30 H3 17 I Comparator_E0 input 1
C0.2 29 G3 N/A I Comparator_E0 input 2
C0.3 28 J2 N/A I Comparator_E0 input 3
C0.4 27 H2 N/A I Comparator_E0 input 4
C0.5 26 J1 N/A I Comparator_E0 input 5
C0.6 25 N/A N/A I Comparator_E0 input 6
C0.7 24 N/A N/A I Comparator_E0 input 7
C1.0 81 B7 50 I Comparator_E1 input 0
C1.1 80 B8 49 I Comparator_E1 input 1
C1.2 79 A7 N/A I Comparator_E1 input 2
C1.3 78 A8 N/A I Comparator_E1 input 3
C1.4 77 B9 N/A I Comparator_E1 input 4
C1.5 76 A9 N/A I Comparator_E1 input 5
C1.6 71 C9 46 I Comparator_E1 input 6
C1.7 70 D9 45 I Comparator_E1 input 7
Debug SWCLKTCK 95 A2 64 I Serial wire clock input (SWCLK)/JTAG clock input (TCK)
SWDIOTMS 94 B2 63 I/O Serial wire data input/output (SWDIO)/JTAG test mode select (TMS)
SWO 93 A3 62 O Serial wire trace output
TDI 92 B3 61 I JTAG test data input
TDO 93 A3 62 O JTAG test data output
GPIO P1.0 4 A1 1 I/O General-purpose digital I/O with port interrupt, wake-up, and glitch filtering capability
P1.1 5 B1 2 I/O General-purpose digital I/O with port interrupt and wake-up capability
P1.2 6 C4 3 I/O General-purpose digital I/O with port interrupt and wake-up capability
P1.3 7 D4 4 I/O General-purpose digital I/O with port interrupt and wake-up capability
P1.4 8 D3 5 I/O General-purpose digital I/O with port interrupt, wake-up, and glitch filtering capability
P1.5 9 C1 6 I/O General-purpose digital I/O with port interrupt, wake-up, and glitch filtering capability
P1.6 10 D1 7 I/O General-purpose digital I/O with port interrupt and wake-up capability
P1.7 11 E1 8 I/O General-purpose digital I/O with port interrupt and wake-up capability
GPIO (continued) P2.0 16 E4 13 I/O General-purpose digital I/O with port interrupt and wake-up capability and with reconfigurable port mapping secondary function. This I/O can be configured for high drive operation with up to 20-mA drive capability.
P2.1 17 F1 14 I/O General-purpose digital I/O with port interrupt and wake-up capability and with reconfigurable port mapping secondary function. This I/O can be configured for high drive operation with up to 20-mA drive capability.
P2.2 18 E3 15 I/O General-purpose digital I/O with port interrupt and wake-up capability and with reconfigurable port mapping secondary function. This I/O can be configured for high drive operation with up to 20-mA drive capability.
P2.3 19 F4 16 I/O General-purpose digital I/O with port interrupt and wake-up capability and with reconfigurable port mapping secondary function. This I/O can be configured for high drive operation with up to 20-mA drive capability.
P2.4 20 F3 N/A I/O General-purpose digital I/O with port interrupt and wake-up capability and with reconfigurable port mapping secondary function
P2.5 21 G1 N/A I/O General-purpose digital I/O with port interrupt and wake-up capability and with reconfigurable port mapping secondary function
P2.6 22 G2 N/A I/O General-purpose digital I/O with port interrupt and wake-up capability and with reconfigurable port mapping secondary function
P2.7 23 H1 N/A I/O General-purpose digital I/O with port interrupt and wake-up capability and with reconfigurable port mapping secondary function
P3.0 32 J3 19 I/O General-purpose digital I/O with port interrupt, wake-up, and glitch filtering capability, and with reconfigurable port mapping secondary function
P3.1 33 H4 20 I/O General-purpose digital I/O with port interrupt and wake-up capability and with reconfigurable port mapping secondary function
P3.2 34 G5 21 I/O General-purpose digital I/O with port interrupt and wake-up capability and with reconfigurable port mapping secondary function
P3.3 35 J4 22 I/O General-purpose digital I/O with port interrupt and wake-up capability and with reconfigurable port mapping secondary function
P3.4 36 H5 23 I/O General-purpose digital I/O with port interrupt, wake-up, and glitch filtering capability, and with reconfigurable port mapping secondary function
P3.5 37 G6 24 I/O General-purpose digital I/O with port interrupt, wake-up, and glitch filtering capability, and with reconfigurable port mapping secondary function
P3.6 38 J5 25 I/O General-purpose digital I/O with port interrupt and wake-up capability and with reconfigurable port mapping secondary function
P3.7 39 H6 26 I/O General-purpose digital I/O with port interrupt and wake-up capability and with reconfigurable port mapping secondary function
GPIO (continued) P4.0 56 H9 N/A I/O General-purpose digital I/O with port interrupt and wake-up capability
P4.1 57 H8 N/A I/O General-purpose digital I/O with port interrupt and wake-up capability
P4.2 58 G7 33 I/O General-purpose digital I/O with port interrupt and wake-up capability
P4.3 59 G8 34 I/O General-purpose digital I/O with port interrupt and wake-up capability
P4.4 60 G9 35 I/O General-purpose digital I/O with port interrupt and wake-up capability
P4.5 61 F7 36 I/O General-purpose digital I/O with port interrupt and wake-up capability
P4.6 62 F8 37 I/O General-purpose digital I/O with port interrupt and wake-up capability
P4.7 63 F9 38 I/O General-purpose digital I/O with port interrupt and wake-up capability
P5.0 64 E7 39 I/O General-purpose digital I/O with port interrupt and wake-up capability
P5.1 65 E8 40 I/O General-purpose digital I/O with port interrupt and wake-up capability
P5.2 66 E9 41 I/O General-purpose digital I/O with port interrupt and wake-up capability
P5.3 67 D7 42 I/O General-purpose digital I/O with port interrupt and wake-up capability
P5.4 68 D8 43 I/O General-purpose digital I/O with port interrupt and wake-up capability
P5.5 69 C8 44 I/O General-purpose digital I/O with port interrupt and wake-up capability
P5.6 70 D9 45 I/O General-purpose digital I/O with port interrupt and wake-up capability
P5.7 71 C9 46 I/O General-purpose digital I/O with port interrupt and wake-up capability
P6.0 54 J9 N/A I/O General-purpose digital I/O with port interrupt and wake-up capability
P6.1 55 H7 N/A I/O General-purpose digital I/O with port interrupt and wake-up capability
P6.2 76 A9 N/A I/O General-purpose digital I/O with port interrupt and wake-up capability
P6.3 77 B9 N/A I/O General-purpose digital I/O with port interrupt and wake-up capability
P6.4 78 A8 N/A I/O General-purpose digital I/O with port interrupt and wake-up capability
P6.5 79 A7 N/A I/O General-purpose digital I/O with port interrupt and wake-up capability
P6.6 80 B8 49 I/O General-purpose digital I/O with port interrupt, wake-up, and glitch filtering capability
P6.7 81 B7 50 I/O General-purpose digital I/O with port interrupt, wake-up, and glitch filtering capability
GPIO (continued) P7.0 88 B5 57 I/O General-purpose digital I/O with reconfigurable port mapping secondary function (RD)
P7.1 89 C5 58 I/O General-purpose digital I/O with reconfigurable port mapping secondary function (RD)
P7.2 90 B4 59 I/O General-purpose digital I/O with reconfigurable port mapping secondary function (RD)
P7.3 91 A4 60 I/O General-purpose digital I/O with reconfigurable port mapping secondary function (RD)
P7.4 26 J1 N/A I/O General-purpose digital I/O with reconfigurable port mapping secondary function (RD)
P7.5 27 H2 N/A I/O General-purpose digital I/O with reconfigurable port mapping secondary function (RD)
P7.6 28 J2 N/A I/O General-purpose digital I/O with reconfigurable port mapping secondary function (RD)
P7.7 29 G3 N/A I/O General-purpose digital I/O with reconfigurable port mapping secondary function (RD)
P8.0 30 H3 17 I/O General-purpose digital I/O
P8.1 31 G4 18 I/O General-purpose digital I/O
P8.2 46 N/A N/A I/O General-purpose digital I/O
P8.3 47 N/A N/A I/O General-purpose digital I/O
P8.4 48 N/A N/A I/O General-purpose digital I/O
P8.5 49 N/A N/A I/O General-purpose digital I/O
P8.6 50 N/A N/A I/O General-purpose digital I/O
P8.7 51 N/A N/A I/O General-purpose digital I/O
P9.0 52 N/A N/A I/O General-purpose digital I/O
P9.1 53 N/A N/A I/O General-purpose digital I/O
P9.2 74 N/A N/A I/O General-purpose digital I/O
P9.3 75 N/A N/A I/O General-purpose digital I/O
P9.4 96 N/A N/A I/O General-purpose digital I/O
P9.5 97 N/A N/A I/O General-purpose digital I/O
P9.6 98 N/A N/A I/O General-purpose digital I/O
P9.7 99 N/A N/A I/O General-purpose digital I/O
P10.0 100 N/A N/A I/O General-purpose digital I/O
P10.1 1 N/A N/A I/O General-purpose digital I/O
P10.2 2 N/A N/A I/O General-purpose digital I/O
P10.3 3 N/A N/A I/O General-purpose digital I/O
P10.4 24 N/A N/A I/O General-purpose digital I/O
P10.5 25 N/A N/A I/O General-purpose digital I/O
PJ.0 41 J6 28 I/O General-purpose digital I/O
PJ.1 42 J7 29 I/O General-purpose digital I/O
PJ.2 85 A6 54 I/O General-purpose digital I/O
PJ.3 86 A5 55 I/O General-purpose digital I/O
PJ.4 92 B3 61 I/O General-purpose digital I/O
PJ.5 93 A3 62 I/O General-purpose digital I/O
I2C UCB0SCL 11 E1 8 I/O I2C clock – eUSCI_B0 I2C mode
UCB0SDA 10 D1 7 I/O I2C data – eUSCI_B0 I2C mode
UCB1SCL 79 A7 N/A I/O I2C clock – eUSCI_B1 I2C mode
UCB1SDA 78 A8 N/A I/O I2C data – eUSCI_B1 I2C mode
UCB3SCL 3 N/A N/A I/O I2C clock – eUSCI_B3 I2C mode
UCB3SCL 81 B7 50 I/O I2C clock – eUSCI_B3 I2C mode
UCB3SDA 2 N/A N/A I/O I2C data – eUSCI_B3 I2C mode
UCB3SDA 80 B8 49 I/O I2C data – eUSCI_B3 I2C mode
Port Mapper PM_C0OUT 89 C5 58 O Default mapping: Comparator_E0 output
PM_C1OUT 90 B4 59 O Default mapping: Comparator_E1 output
PM_DMAE0 88 B5 57 I Default mapping: DMA external trigger input
PM_SMCLK 88 B5 57 O Default mapping: SMCLK clock output
PM_TA0.0 91 A4 60 I/O Default mapping: TA0 CCR0 capture: CCI0A input, compare: Out0
PM_TA0.1 20 F3 N/A I/O Default mapping: TA0 CCR1 capture: CCI1A input, compare: Out1
PM_TA0.2 21 G1 N/A I/O Default mapping: TA0 CCR2 capture: CCI2A input, compare: Out2
PM_TA0.3 22 G2 N/A I/O Default mapping: TA0 CCR3 capture: CCI3A input, compare: Out3
PM_TA0.4 23 H1 N/A I/O Default mapping: TA0 CCR4 capture: CCI4A input, compare: Out4
PM_TA0CLK 89 C5 58 I Default mapping: TA0 input clock
PM_TA1.2 28 J2 N/A I/O Default mapping: TA1 CCR2 capture: CCI2A input, compare: Out2
PM_TA1.3 27 H2 N/A I/O Default mapping: TA1 CCR3 capture: CCI3A input, compare: Out3
PM_TA1.4 26 J1 N/A I/O Default mapping: TA1 CCR4 capture: CCI4A input, compare: Out4
PM_TA1CLK 90 B4 59 I Default mapping: TA1 input clock
PM_UCA1CLK 17 F1 14 I/O Default mapping: Clock signal input – eUSCI_A1 SPI slave mode
Clock signal output – eUSCI_A1 SPI master mode
PM_UCA1RXD 18 E3 15 I Default mapping: Receive data – eUSCI_A1 UART mode
PM_UCA1SIMO 19 F4 16 I/O Default mapping: Slave in, master out – eUSCI_A1 SPI mode
PM_UCA1SOMI 18 E3 15 I/O Default mapping: Slave out, master in – eUSCI_A1 SPI mode
PM_UCA1STE 16 E4 13 I/O Default mapping: Slave transmit enable – eUSCI_A1 SPI mode
PM_UCA1TXD 19 F4 16 O Default mapping: Transmit data – eUSCI_A1 UART mode
PM_UCA2CLK 33 H4 20 I/O Default mapping: Clock signal input – eUSCI_A2 SPI slave mode
Clock signal output – eUSCI_A2 SPI master mode
PM_UCA2RXD 34 G5 21 I Default mapping: Receive data – eUSCI_A2 UART mode
PM_UCA2SIMO 35 J4 22 I/O Default mapping: Slave in, master out – eUSCI_A2 SPI mode
PM_UCA2SOMI 34 G5 21 I/O Default mapping: Slave out, master in – eUSCI_A2 SPI mode
PM_UCA2STE 32 J3 19 I/O Default mapping: Slave transmit enable – eUSCI_A2 SPI mode
PM_UCA2TXD 35 J4 22 O Default mapping: Transmit data – eUSCI_A2 UART mode
Port Mapper (continued) PM_UCB2CLK 37 G6 24 I/O Default mapping: Clock signal input – eUSCI_B2 SPI slave mode
Clock signal output – eUSCI_B2 SPI master mode
PM_UCB2SCL 39 H6 26 I Default mapping: I2C clock – eUSCI_B2 I2C mode
PM_UCB2SDA 38 J5 25 I/O Default mapping: I2C data – eUSCI_B2 I2C mode
PM_UCB2SIMO 38 J5 25 I/O Default mapping: Slave in, master out – eUSCI_B2 SPI mode
PM_UCB2SOMI 39 H6 26 I/O Default mapping: Slave out, master in – eUSCI_B2 SPI mode
PM_UCB2STE 36 H5 23 I/O Default mapping: Slave transmit enable – eUSCI_B2 SPI mode
Power AVCC1 45 F6 32 Analog power supply
AVCC2 87 D5 56 Analog power supply
AVSS1 43 F5 30 Analog ground supply
AVSS2 84 D6 53 Analog ground supply
AVSS3 40 E5 27 Analog ground supply
DVCC1 13 D2 10 Digital power supply
DVCC2 73 C6 48 Digital power supply
DVSS1 15 F2 12 Digital ground supply
DVSS2 72 E6 47 Digital ground supply
DVSS3 82 C7 51 Must be connected to ground
VCORE(3) 12 C2 9 Regulated core power supply (internal use only, no external current loading)
VSW 14 E2 11 DC-to-DC converter switching output
RTC RTCCLK 59 G8 34 O RTC_C clock calibration output
Reference VREF+ 70 D9 45 O Internal shared reference voltage positive terminal
VREF- 71 C9 46 O Internal shared reference voltage negative terminal
VeREF+ 70 D9 45 I Positive terminal of external reference voltage to ADC
VeREF- 71 C9 46 I Negative terminal of external reference voltage to ADC (recommended to connect to onboard ground)
SPI UCA0CLK 5 B1 2 I/O Clock signal input – eUSCI_A0 SPI slave mode
Clock signal output – eUSCI_A0 SPI master mode
UCA0SIMO 7 D4 4 I/O Slave in, master out – eUSCI_A0 SPI mode
UCA0SOMI 6 C4 3 I/O Slave out, master in – eUSCI_A0 SPI mode
UCA0STE 4 A1 1 I/O Slave transmit enable – eUSCI_A0 SPI mode
UCA3CLK 97 N/A N/A I/O Clock signal input – eUSCI_A3 SPI slave mode
Clock signal output – eUSCI_A3 SPI master mode
UCA3SIMO 99 N/A N/A I/O Slave in, master out – eUSCI_A3 SPI mode
UCA3SOMI 98 N/A N/A I/O Slave out, master in – eUSCI_A3 SPI mode
UCA3STE 96 N/A N/A I/O Slave transmit enable – eUSCI_A3 SPI mode
UCB0CLK 9 C1 6 I/O Clock signal input – eUSCI_B0 SPI slave mode
Clock signal output – eUSCI_B0 SPI master mode
UCB0SIMO 10 D1 7 I/O Slave in, master out – eUSCI_B0 SPI mode
UCB0SOMI 11 E1 8 I/O Slave out, master in – eUSCI_B0 SPI mode
UCB0STE 8 D3 5 I/O Slave transmit enable – eUSCI_B0 SPI mode
UCB1CLK 77 B9 N/A I/O Clock signal input – eUSCI_B1 SPI slave mode
Clock signal output – eUSCI_B1 SPI master mode
UCB1SIMO 78 A8 N/A I/O Slave in, master out – eUSCI_B1 SPI mode
UCB1SOMI 79 A7 N/A I/O Slave out, master in – eUSCI_B1 SPI mode
UCB1STE 76 A9 N/A I/O Slave transmit enable – eUSCI_B1 SPI mode
UCB3CLK 1 N/A N/A I/O Clock signal input – eUSCI_B3 SPI slave mode
Clock signal output – eUSCI_B3 SPI master mode
UCB3CLK 31 G4 18 I/O Clock signal input – eUSCI_B3 SPI slave mode
Clock signal output – eUSCI_B3 SPI master mode
UCB3SIMO 2 N/A N/A I/O Slave in, master out – eUSCI_B3 SPI mode
UCB3SIMO 80 B8 49 I/O Slave in, master out – eUSCI_B3 SPI mode
UCB3SOMI 3 N/A N/A I/O Slave out, master in – eUSCI_B3 SPI mode
UCB3SOMI 81 B7 50 I/O Slave out, master in – eUSCI_B3 SPI mode
UCB3STE 30 H3 17 I/O Slave transmit enable – eUSCI_B3 SPI mode
UCB3STE 100 N/A N/A I/O Slave transmit enable – eUSCI_B3 SPI mode
System NMI 83 B6 52 I External nonmaskable interrupt
RSTn 83 B6 52 I External reset (active low)
SVMHOUT 60 G9 35 O SVMH output
Thermal QFN Pad N/A N/A Pad QFN package exposed thermal pad. TI recommends connection to VSS.
Timer PM_TA1.1 29 G3 N/A I/O Default mapping: TA1 CCR1 capture: CCI1A input, compare: Out1
TA1.0 30 H3 17 I/O TA1 CCR0 capture: CCI0A input, compare: Out0
TA2.0 31 G4 18 I/O TA2 CCR0 capture: CCI0A input, compare: Out0
TA2.1 70 D9 45 I/O TA2 CCR1 capture: CCI1A input, compare: Out1
TA2.2 71 C9 46 I/O TA2 CCR2 capture: CCI2A input, compare: Out2
TA2.3 80 B8 49 I/O TA2 CCR3 capture: CCI3A input, compare: Out3
TA2.4 81 B7 50 I/O TA2 CCR4 capture: CCI4A input, compare: Out4
TA2CLK 58 G7 33 I TA2 input clock
TA3.0 24 N/A N/A I/O TA3 CCR0 capture: CCI0A input, compare: Out0
TA3.1 25 N/A N/A I/O TA3 CCR1 capture: CCI1A input, compare: Out1
TA3.2 46 N/A N/A I/O TA3 CCR2 capture: CCI2A input, compare: Out2
TA3.3 74 N/A N/A I/O TA3 CCR3 capture: CCI3A input, compare: Out3
TA3.4 75 N/A N/A I/O TA3 CCR4 capture: CCI4A input, compare: Out4
TA3CLK 47 N/A N/A I TA3 input clock
UART UCA0RXD 6 C4 3 I Receive data – eUSCI_A0 UART mode
UCA0TXD 7 D4 4 O Transmit data – eUSCI_A0 UART mode
UCA3RXD 98 N/A N/A I Receive data – eUSCI_A3 UART mode
UCA3TXD 99 N/A N/A O Transmit data – eUSCI_A3 UART mode
I = input, O = output
N/A = not available
VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended capacitor value, CVCORE.