Refer to the PDF data sheet for device specific package drawings
The application can optimize the leakage power consumption of the SRAM in LPM3 and LPM4 modes of operation. To enable this, each SRAM bank can be individually configured for retention. Banks that are enabled for retention retain their data through the LPM3 and LPM4 modes. The application can also retain a subset of the enabled banks.
For example, the application may need 32KB of SRAM for its processing needs (four banks are kept enabled). However, of these four banks, only one bank may contain critical data that must be retained in LPM3 or LPM4, while the rest are powered off completely to minimize power consumption.
Bank 0 of the SRAM is always retained and cannot be powered down. Therefore, it also operates up as a possible backup memory in the LPM3, LPM4, and LPM3.5 modes of operation. In the case of LPM3 and LPM4 modes, the full 8KB of SRAM bank 0 is retained but in the case of LPM3.5 mode only 6KB of SRAM bank 0 is retained. The 2KB of SRAM bank 0 over the address range 0x2000_0000 to 0x2000_07FF is not retained in LPM3.5 mode.