The flash memory provides multiple read and program modes of operation that the application can deploy. Up to 128 bits (memory word width) can be programmed (set from 1 to 0) in a single program operation. Although the CPU data buses are 32 bits wide, the flash can buffer 128-bit write data before initiating flash programming, thereby making it more seamless and power efficient for software to program large blocks of data at a time. In addition, the flash memory also supports a burst write mode that takes less time when compared to programming words individually. See for information on timing parameters.
The flash main and information memory regions offer write/erase protection control at a sector granularity to enable software to optimize operations like mass erase while protecting certain regions of the flash. In low-power modes of operation, the flash memory is disabled and put in a power-down state to minimize leakage.
For details on the flash memory and its various modes of operation and configuration, see the Flash Controller A (FLCTL_A) chapter in the MSP432P4xx SimpleLink™ Microcontrollers Technical Reference Manual.
Depending on the CPU (MCLK) frequency and the active mode in use, the flash may need to be accessed with single/multiple wait states. Whenever there is a change required in the operating frequency, the application must ensure that the flash access wait states are configured correctly before making the frequency change. See the electrical specification for details on flash wait state requirements.