SLASF12D February   2023  – October 2025 MSPM0G3105 , MSPM0G3106 , MSPM0G3107

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Ramp
      1. 7.6.1 POR and BOR
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
        1. 7.9.1.1 SYSOSC Typical Frequency Accuracy
      2. 7.9.2 Low Frequency Oscillator (LFOSC)
      3. 7.9.3 System Phase Lock Loop (SYSPLL)
      4. 7.9.4 Low Frequency Crystal/Clock
      5. 7.9.5 High Frequency Crystal/Clock
    10. 7.10 Digital IO
      1. 7.10.1 Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 Analog Mux VBOOST
    12. 7.12 ADC
      1. 7.12.1 Electrical Characteristics
      2. 7.12.2 Switching Characteristics
      3. 7.12.3 Linearity Parameters
    13. 7.13 Typical Connection Diagram
    14. 7.14 Temperature Sensor
    15. 7.15 VREF
      1. 7.15.1 Voltage Characteristics
      2. 7.15.2 Electrical Characteristics
    16. 7.16 GPAMP
      1. 7.16.1 Electrical Characteristics
      2. 7.16.2 Switching Characteristics
    17. 7.17 I2C
      1. 7.17.1 I2C Timing Diagram
      2. 7.17.2 I2C Characteristics
      3. 7.17.3 I2C Filter
    18. 7.18 SPI
      1. 7.18.1 SPI
      2. 7.18.2 SPI Timing Diagram
    19. 7.19 UART
    20. 7.20 TIMx
    21. 7.21 TRNG
      1. 7.21.1 TRNG Electrical Characteristics
      2. 7.21.2 TRNG Switching Characteristics
    22. 7.22 Emulation and Debug
      1. 7.22.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  CPU
    2. 8.2  Operating Modes
      1. 8.2.1 Functionality by Operating Mode (MSPM0G310x)
    3. 8.3  Power Management Unit (PMU)
    4. 8.4  Clock Module (CKM)
    5. 8.5  DMA
    6. 8.6  Events
    7. 8.7  Memory
      1. 8.7.1 Memory Organization
      2. 8.7.2 Peripheral File Map
      3. 8.7.3 Peripheral Interrupt Vector
    8. 8.8  Flash Memory
    9. 8.9  SRAM
    10. 8.10 GPIO
    11. 8.11 IOMUX
    12. 8.12 ADC
    13. 8.13 Temperature Sensor
    14. 8.14 VREF
    15. 8.15 GPAMP
    16. 8.16 TRNG
    17. 8.17 AES
    18. 8.18 CRC
    19. 8.19 UART
    20. 8.20 I2C
    21. 8.21 SPI
    22. 8.22 CAN-FD
    23. 8.23 WWDT
    24. 8.24 RTC
    25. 8.25 Timers (TIMx)
    26. 8.26 Device Analog Connections
    27. 8.27 Input/Output Diagrams
    28. 8.28 Serial Wire Debug Interface
    29. 8.29 Bootstrap Loader (BSL)
    30. 8.30 Device Factory Constants
    31. 8.31 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.8 Timing Characteristics

VDD=3.3V, Ta=25℃ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Wakeup Timing
tWAKE, SLEEP0 Wakeup time from SLEEP0 to RUN (1) 1.3 us
tWAKE, SLEEP1 Wakeup time from SLEEP1 to RUN (1) 1.5 us
tWAKE, SLEEP2 Wakeup time from SLEEP2 to RUN (1) 2.1 us
tWAKE, STANDBY0 Wakeup time from STANDBY0 to RUN (1) 15.2 us
tWAKE, STANDBY1 Wakeup time from STANDBY1 to RUN (1) 15.2 us
tWAKE, STOP0 Wakeup time from STOP0 to RUN (SYSOSC enabled) (1) 12.1 us
tWAKE, STOP1 Wakeup time from STOP1 to RUN (SYSOSC enabled) (1) 13.5 us
tWAKE, STOP2 Wakeup time from STOP2 to RUN (SYSOSC disabled) (1) 12.9
tWAKEUP, SHDN Wakeup time from SHUTDOWN to RUN (2) Fast boot enabled 240 us
Fast boot disabled 252
Asynchronous Fast Clock Request Timing
tDELAY, SLEEP1 Delay time from edge of asynchronous request to first 32MHz MCLK edge Mode is SLEEP1 0.33 us
tDELAY, SLEEP2 Delay time from edge of asynchronous request to first 32MHz MCLK edge Mode is SLEEP2 0.93 us
tDELAY, STANDBY0 Delay time from edge of asynchronous request to first 32MHz MCLK edge Mode is STANDBY0 3.2 us
tDELAY, STANDBY1 Delay time from edge of asynchronous request to first 32MHz MCLK edge Mode is STANDBY1 3.2 us
tDELAY, STOP0 Delay time from edge of asynchronous request to first 32MHz MCLK edge Mode is STOP0 0.1 us
tDELAY, STOP1 Delay time from edge of asynchronous request to first 32MHz MCLK edge Mode is STOP1 2.4 us
tDELAY, STOP2 Delay time from edge of asynchronous request to first 32MHz MCLK edge Mode is STOP2 0.9 us
Startup Timing
tSTART, RESET Device cold startup time from reset/power-up (3) Fast boot enabled 260 us
Fast boot disabled 308
NRST Timing
tRST, BOOTRST Pulse length on NRST pin to generate BOOTRST ULPCLK≥4MHz 1.5 us
ULPCLK=32kHz 80
tRST, POR Pulse length on NRST pin to generate POR 1 s
(1) The wake-up time is measured from the edge of an external wake-up signal (GPIO wake-up event) to the time that the first instruction of the user program is executed, with glitch filter disabled (FILTEREN=0x0) and fast wake enabled (FASTWAKEONLY=1) .
(2) The wake-up time is measured from the edge of an external wake-up signal (IOMUX wake-up event) to the time that first instruction of the user program is executed.
(3) The start-up time is measured from the time that VDD crosses VBOR0- (cold start-up) to the time that the first instruction of the user program is executed.