SLASFA2B November   2024  – October 2025 MSPM0G1518 , MSPM0G1519 , MSPM0G3518 , MSPM0G3519

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
    1. 5.1 Device Comparison Chart
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
      1.      11
    3. 6.3 Signal Descriptions
      1.      13
      2.      14
      3.      15
      4.      16
      5.      17
      6.      18
      7.      19
      8.      20
      9.      21
      10.      22
      11.      23
      12.      24
      13.      25
      14.      26
      15.      27
      16.      28
      17.      29
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Sequencing
      1. 7.6.1 Power Supply Ramp
      2. 7.6.2 POR and BOR
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
      2. 7.9.2 Low Frequency Oscillator (LFOSC)
      3. 7.9.3 System Phase Lock Loop (SYSPLL)
      4. 7.9.4 Low Frequency Crystal/Clock
      5. 7.9.5 High Frequency Crystal/Clock
    10. 7.10 Digital IO
      1. 7.10.1  Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 Analog Mux VBOOST
    12. 7.12 ADC
      1. 7.12.1 Electrical Characteristics
      2. 7.12.2 Switching Characteristics
      3. 7.12.3 Linearity Parameters
      4. 7.12.4 Typical Connection Diagram
    13. 7.13 Temperature Sensor
    14. 7.14 VREF
      1. 7.14.1 Voltage Characteristics
      2. 7.14.2 Electrical Characteristics
    15. 7.15 Comparator (COMP)
      1. 7.15.1 Comparator Electrical Characteristics
    16. 7.16 DAC
      1. 7.16.1 DAC_Supply Specifications
      2. 7.16.2 DAC Output Specifications
      3. 7.16.3 DAC Dynamic Specifications
      4. 7.16.4 DAC Linearity Specifications
      5. 7.16.5 DAC Timing Specifications
    17. 7.17 I2C
      1. 7.17.1 I2C Characteristics
      2. 7.17.2 I2C Filter
      3. 7.17.3 I2C Timing Diagram
    18. 7.18 SPI
      1. 7.18.1 SPI
      2. 7.18.2 SPI Timing Diagram
    19. 7.19 UART
    20. 7.20 TIMx
    21. 7.21 TRNG
      1. 7.21.1 TRNG Electrical Characteristics
      2. 7.21.2 TRNG Switching Characteristics
    22. 7.22 Emulation and Debug
      1. 7.22.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  Functional Block Diagram
    2. 8.2  CPU
    3. 8.3  Operating Modes
      1. 8.3.1 Functionality by Operating Mode (MSPM0Gx51x)
    4. 8.4  Power Management Unit (PMU)
    5. 8.5  Clock Module (CKM)
    6. 8.6  DMA
    7. 8.7  Events
    8. 8.8  Memory
      1. 8.8.1 Memory Organization
      2. 8.8.2 Peripheral File Map
      3. 8.8.3 Peripheral Interrupt Vector
    9. 8.9  Flash Memory
    10. 8.10 SRAM
    11. 8.11 GPIO
    12. 8.12 IOMUX
    13. 8.13 ADC
    14. 8.14 Temperature Sensor
    15. 8.15 VREF
    16. 8.16 COMP
    17. 8.17 DAC
    18. 8.18 Security
    19. 8.19 TRNG
    20. 8.20 AESADV
    21. 8.21 Keystore
    22. 8.22 CRC-P
    23. 8.23 MATHACL
    24. 8.24 UART
    25. 8.25 I2C
    26. 8.26 SPI
    27. 8.27 CAN-FD
    28. 8.28 Low-Frequency Sub System (LFSS)
    29. 8.29 RTC_B
    30. 8.30 IWDT_B
    31. 8.31 WWDT
    32. 8.32 Timers (TIMx)
    33. 8.33 Device Analog Connections
    34. 8.34 Input/Output Diagrams
    35. 8.35 Serial Wire Debug Interface
    36. 8.36 Boot Strap Loader (BSL)
    37. 8.37 Device Factory Constants
    38. 8.38 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tray Information
    2.     PACKAGE OPTION ADDENDUM

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZAW|100
  • PM|64
  • RGZ|48
  • RHB|32
  • PN|80
  • PZ|100
  • PT|48
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Table 6-6 Comparator (COMP) Signal Descriptions
SIGNAL
NAME		PIN
TYPE		DESCRIPTIONRHB PINZAW PINYCJ PINRGZ PINPT PINPM PINPN PINPZ PIN
COMP0_OUTOCOMP0 digital output signal11, 15, 16, 20, 29, 31, 7A6, B1, B2, B7, C1, D1, D2, E9, F10, F9, G1, H7, J1, J10A4, A5, B1, C4, C5, D2, E4, F3, G213, 19, 22, 27, 31, 38, 45, 47, 913, 19, 22, 27, 31, 38, 45, 47, 916, 22, 26, 27, 28, 29, 31, 43, 49, 5, 57, 60, 62, 911, 17, 29, 32, 34, 41, 45, 60, 70, 74, 75, 76, 77, 7916, 22, 34, 42, 44, 51, 55, 75, 85, 94, 95, 96, 97, 99
COMP1_OUTOCOMP1 digital output signal7A6, F10, F9B1, C422, 922, 943, 60, 6211, 32, 3416, 42, 44
COMP2_OUTOCOMP2 digital output signal20D2, H7, J1C5, E431, 3831, 3816, 29, 945, 60, 7755, 75, 97
COMP0_IN0+ACOMP0 non-inverting input channel 030C2G34646307898
COMP0_IN0-ACOMP0 inverting input channel 031B2G24747317999
COMP0_IN1+ACOMP0 non-inverting input channel 122K3E53333115570
COMP0_IN1-ACOMP0 inverting input channel 121K4D43232105469
COMP0_IN2+ACOMP0 non-inverting input channel 218K8B5292974353
COMP0_IN2-ACOMP0 inverting input channel 217K10A6282864252
COMP0_IN3+ACOMP0 non-inverting input channel 319K7B6303084454
COMP1_IN0+ACOMP1 non-inverting input channel 0B1287696
COMP1_IN0-ACOMP1 inverting input channel 0D2297797
COMP1_IN1+ACOMP1 non-inverting input channel 1F24242237186
COMP1_IN1-ACOMP1 inverting input channel 127E1G44343247292
COMP1_IN2+ACOMP1 non-inverting input channel 2K1D53737155974
COMP1_IN2-ACOMP1 inverting input channel 2K2G63636145873
COMP1_IN3+ACOMP1 non-inverting input channel 319K7B6303084454
COMP2_IN0+ACOMP2 non-inverting input channel 0G2206883
COMP2_IN0-ACOMP2 inverting input channel 0H1216984
COMP2_IN1+ACOMP2 non-inverting input channel 1J1E43838166075
COMP2_IN1-ACOMP2 inverting input channel 125J2G53939176176