MSPM0 MCUs include a low power, high performance SRAM memory with zero wait state access across the supported CPU frequency range of the device. MSPM0 MCUs also provides up to 128KB SRAM. SRAM memory may be used for storing volatile information such as the call stack, heap, global data, and code.

The SRAM memory content is split into two banks of 64kB each. SRAM (Bank 0) provides 64kB of ECC or parity protected SRAM and is always available in run, sleep, stop, and standby operating modes. SRAM (Bank 1) provides 64kB which does not include ECC protection or parity and can be selectively enabled or disabled through BANKOFF1 bit in SRAMCFG register in SYSCTL. When enabled, SRAM (Bank 1) is available in run, sleep, and stop modes. SRAM (Bank 1) can be powered off in STOP mode by configuring the BANKSTOP1 bit in SRAMCFG register in SYSCTL. SRAM contents for both banks are lost in shutdown mode.

A write-execute mutual exclusion mechanism is provided to allow the application to partition the SRAM into three sections: two read-write (RW) partitions and a read-execute (RX) partition. The two RW partitions occupy the low and high portions of SRAM address space, while the RX partition occupies the middle portion of the SRAM address space. The SRAMBOUNDARY and SRAMBOUNDARYHIGH registers in SYSCTL need to be configured to set up these partitions. Write protection is useful when placing executable code into SRAM as it provides a level of protection against unintentional overwrites of code by either the CPU or DMA. Placing code in SRAM can improve performance of critical loops by enabling zero wait state operation and lower power consumption. Preventing code execution from the RW partition improves security by preventing self-modifying code execution ability.