SBOS900B September   2018  – June 2019 OPA2156

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Low Input Voltage Noise Spectral Density
      2.      OPA2156 Transimpedance Configuration
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information: OPA2156
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Phase Reversal Protection
      2. 7.3.2 Electrical Overstress
      3. 7.3.3 Thermal Considerations
      4. 7.3.4 Thermal Shutdown
      5. 7.3.5 Common-Mode Voltage Range
      6. 7.3.6 Overload Recovery
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Slew Rate Limit for Input Protection
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Power Dissipation
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 TINA-TI (Free Software Download)
        2. 11.1.1.2 TI Precision Designs
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Typical Characteristics

Table 1. Table of Graphs

DESCRIPTION FIGURE
Offset Voltage Production Distribution Figure 1
Offset Voltage vs Temperature (PMOS) Figure 2
Offset Voltage vs Temperature (NMOS) Figure 3
Offset Voltage vs Power Supply Figure 4
Offset Voltage vs Common-Mode Voltage Figure 5
Offset Voltage vs Common-Mode Voltage in Transition Region Figure 6
Offset Voltage Drift Figure 7
Input Voltage Noise Spectral Density Figure 8
0.1-Hz to 10-Hz Noise Figure 9
THD+N vs Frequency Figure 10
THD+N vs Output Amplitude Figure 11
Input Bias and Offset Current vs Common-Mode Voltage Figure 12
Input Bias and Offset Current vs Temperature Figure 13
Input Bias and Offset Current vs Temperature Figure 14
Open-Loop Output Impedance vs Frequency Figure 15
Maximum Output Voltage vs Frequency Figure 16
Open-Loop Gain and Phase Vs Frequency Figure 17
Open-Loop Gain vs Temperature Figure 18
Closed-Loop Gain vs Frequency Figure 19
CMRR vs Frequency Figure 20
PSRR vs Frequency Figure 21
CMRR vs Temperature Figure 22
PSRR vs Temperature Figure 23
Positive Output Voltage vs Output Current Figure 24
Negative Output Voltage vs Output Current Figure 26
Short-Circuit Current vs Temperature Figure 25
No Phase Reversal Figure 27
Phase Margin vs Capacitive Load Figure 28
Small-Signal Overshoot vs Capacitive Load (G = –1) Figure 29
Small-Signal Overshoot vs Capacitive Load (G= +1) Figure 30
Settling Time Figure 31
Negative Overload Recovery Figure 32
Positive Overload Recovery Figure 33
Small-Signal Step Response (Noninverting) Figure 34
Small-Signal Step Response (Inverting) Figure 35
Large-Signal Step Response (Noninverting) Figure 36
Large-Signal Step Response (Inverting) Figure 37
Quiescent Current vs Supply Voltage Figure 38
Quiescent Current vs Temperature Figure 39
Channel Separation vs Frequency Figure 40
EMIRR vs Frequency Figure 41
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2, and CL = 30 pF (unless otherwise noted)
OPA2156 D000_Vos distribution_18v_supply.gif
TA = 25°C
Figure 1. Offset Voltage Production Distribution
OPA2156 D016_Vos_vs_Temp_NMOS.gif
NMOS region
Figure 3. Offset Voltage vs Temperature (NMOS)
OPA2156 D017B_Vos_vs_Vcm_Temp_PMOS.gif
Figure 5. Offset Voltage vs Common-Mode Voltage
OPA2156 D003_Vos_Drift_Histo.gif
TA = –40°C to +125°C
Figure 7. Offset Voltage Drift
OPA2156 D027_p1_10Hz_ppNoise.gif
Figure 9. 0.1-Hz to 10-Hz Noise
OPA2156 D010_THDN_Vrms_2Configs_2Loads.gif
1 kHz, 80-kHz measurement bandwidth
Figure 11. THD+N vs Output Amplitude
OPA2156 D022A_Ib_vs_Temp_-55-85.gif
TA = –55°C to +85°C
Figure 13. Input Bias and Offset Current vs Temperature (SOIC)
OPA2156 D011_OpenLoopOutputImpedance.gif
Figure 15. Open-Loop Output Impedance vs Frequency
OPA2156 D004_Aol_Phase_Updated.gif
Figure 17. Open-Loop Gain and Phase vs Frequency
OPA2156 D006_ClosedLoopGain.gif
Figure 19. Closed-Loop Gain vs Frequency
OPA2156 D007B_PSRR_vs_Frequency_Updated.gif
Figure 21. PSRR vs Frequency
OPA2156 D026_PSR_vs_Temp.gif
Figure 23. PSRR vs Temperature
OPA2156 D038_Isc_vs_Temp.gif
Figure 25. Short-Circuit Current vs Temperature
OPA2156 D033_AntiPhaseReversal.gif
Figure 27. No Phase Reversal
OPA2156 D031_Inverting_Overshoot_Vs_Capload.gif
10-mV output step, gain = –1
Figure 29. Small Signal Overshoot vs Capacitive Load
OPA2156 D037_SettlingTime_Updated.gif
Vin = 5-Vpp
Figure 31. Normalized Settling Time
OPA2156 D034A_PositiveOverload.gif
Gain = –10
Figure 33. Positive Overload Recovery
OPA2156 D035B_SmallSignal_10mV_G-1.gif
Vin = 10 mVpp, gain = –1
Figure 35. Small-Signal Step Response (Inverting)
OPA2156 D036B_LargeSignal_10V_G-1.gif
Vin = 5 Vpp, gain = –1
Figure 37. Large Signal Step Response (Inverting)
OPA2156 D029_Iq_vs_Temp.gif
Figure 39. Quiescent Current vs Temperature
OPA2156 D014_EMIRR.gif
Prf =-10 dBm
Figure 41. EMIRR vs Frequency
OPA2156 D015_Vos_vs_Temp_PMOS.gif
PMOS region
Figure 2. Offset Voltage vs Temperature (PMOS)
OPA2156 D020_Vos_vs_Vs.gif
Figure 4. Offset Voltage vs Power Supply
OPA2156 D017A_Vos_vs_Vcm_Temp_TransitionNMOS.gif
Transition between PMOS and NMOS regions
Figure 6. Offset Voltage vs Common-Mode Voltage in Transition Region
OPA2156 D008_VoltageNoise_10MHz.gif
Figure 8. Input Voltage Noise Spectral Density
OPA2156 D009_THDN_Freq_2Configs_2Loads_3p5Vrms.gif
3.5 VRMS, 80-kHz measurement bandwidth
Figure 10. THD+N vs Frequency
OPA2156 D021_Ib_vs_Vcm.gif
Figure 12. Input Bias and Offset Current vs Common-Mode Voltage (SOIC)
OPA2156 D022B_Ib_vs_Temp_50-125.gif
TA = –55°C to +125°C
Figure 14. Input Bias and Offset Current vs Temperature (SOIC)
OPA2156 D012_FullPowerBandwidth.gif
Figure 16. Maximum Output Voltage vs Frequency
OPA2156 D030_AOL_vs_Temp.gif
Figure 18. Open-Loop Gain vs Temperature
OPA2156 D007A_CMRR.gif
Figure 20. CMRR vs Frequency
OPA2156 D025_CMR_vs_Temp_PMOS.gif
Figure 22. CMRR vs Temperature
OPA2156 D023_Claw_Source_18.gif
Figure 24. Positive Output Voltage vs Output Current
OPA2156 D024_Claw_Sink_18.gif
Figure 26. Negative Output Voltage vs Output Current
OPA2156 D005_PhaseMargin_vs_Cload_New.gif
Figure 28. Phase Margin vs Capacitive Load
OPA2156 D032_NonInverting_Overshoot_Vs_Capload.gif
10-mV output step, gain = +1
Figure 30. Small Signal Overshoot vs Capacitive Load
OPA2156 D034A_NegativeOverload.gif
Gain = –10
Figure 32. Negative Overload Recovery
OPA2156 D035A_SmallSignal_10mV_G1.gif
Vin = 10 mVpp, gain = 1
Figure 34. Small-Signal Step Response (Noninverting)
OPA2156 D036A_LargeSignal_10V_G1.gif
Vin = 5 Vpp, gain = 1
Figure 36. Large-Signal Step Response (Noninverting)
OPA2156 D028_Iq_vs_Vs.gif
Figure 38. Quiescent Current vs Supply Voltage
OPA2156 D013_ChannelSeparation_Smooth.gif
Figure 40. Channel Separation vs Frequency