SBOSAA5B April   2022  – September 2022 OPA2675

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Family Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: Full Bias and Offline Mode VS = ±6 V
    6. 7.6  Electrical Characteristics: 75% Bias Mode VS = ±6 V
    7. 7.7  Electrical Characteristics: 50% Bias Mode VS = ±6 V
    8. 7.8  Electrical Characteristics: DIfferential Output  VS = 12 V
    9. 7.9  Electrical Characteristics: VS = 5 V
    10. 7.10 Typical Characteristics: VS = ±6 V, Full Bias
    11. 7.11 Typical Characteristics: VS = ±6 V Differential, Full Bias
    12. 7.12 Typical Characteristics: VS = ±6 V, 75% Bias
    13. 7.13 Typical Characteristics: VS = ±6 V, 50% Bias
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Operating Suggestions
        1. 8.3.1.1 Setting Resistor Values to Optimize Bandwidth
        2. 8.3.1.2 Output Current and Voltage
        3. 8.3.1.3 Driving Capacitive Loads
        4. 8.3.1.4 Line Driver Headroom Model
        5. 8.3.1.5 Noise Performance
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 High-Speed Active Filters
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Thermal Analysis
    2. 10.2 Input and ESD Protection
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Line Driver Headroom Model

The first step in a driver design is to compute the peak-to-peak output voltage from the target specifications. This calculation is done using the following equations:

Equation 2. GUID-1AEA3BC9-D32A-45B3-8018-D8C4B49BB950-low.gif

With PL power and VRMS voltage at the load, and RL load impedance, this calculation gives:

Equation 3. GUID-1D4E1963-0D41-4475-A8E3-C5E45524890C-low.gif
Equation 4. GUID-791E2B71-E3F8-424D-9D6E-167122B79AD7-low.gif

With VP peak voltage at the load and the crest factor, CF:

Equation 5. GUID-80C50F35-9DFC-49CB-9B1A-3DED7C28B6BE-low.gif

With VLPP: peak-to-peak voltage at the load.

Consolidating Equation 2 through Equation 5 allows the required peak-to-peak voltage at the load function of the crest factor, the load impedance, and the power in the load to be expressed. Thus:

Equation 6. GUID-72E45F71-7147-4358-8F7E-7A21F3EA0CD6-low.gif

This VLPP is usually computed for a nominal line impedance and may be taken as a fixed design target.

The next step for the driver is to compute the individual amplifier output voltage and currents as a function of VPP on the line and transformer turns ratio. As the turns ratio changes, the minimum allowed supply voltage also changes. The peak current in the amplifier is given by:

Equation 7. GUID-951DE5E0-9AD3-4D56-9E96-08E6D1285DBE-low.gif

With VLPP defined in Equation 6 and RM defined in Equation 8.

Equation 8. GUID-559948FF-94AF-45ED-92CD-316F8D37C0D3-low.gif

The peak current is computed in Figure 8-9 by noting that the total load is 4RM and that the peak current is half of the peak-to-peak calculated using VLPP.

GUID-6830FFD1-2F1C-4B4F-A159-C65D39D48BB2-low.gif Figure 8-9 Driver Peak Output Model

With the required output voltage and current versus turns ratio set, an output stage headroom model allows the required supply voltage versus turns ratio to be developed.

The headroom model (see Figure 8-10) can be described with the following set of equations:

First, as available output voltage for each amplifier:

Equation 9. GUID-8EA93893-A9DA-4955-9D5B-BC8E71BC8E2F-low.gif

Or, second, as required single-supply voltage:

Equation 10. GUID-525C1FF8-75F3-48B8-AADE-0857A5EE1530-low.gif

The minimum supply voltage for a set of power and load requirements is given by Equation 10, where V1, V2, R1, and R2 are internal to the OPA2675.

Table 8-1 gives V1, V2, R1, and R2 for +12-V operation of the OPA2675.

GUID-A0F174EC-14F4-406F-9F5E-E9E4DE4D4F2C-low.gif Figure 8-10 Line Driver Headroom Model
Table 8-1 Line Driver Headroom Model Values
V1 R1 V2 R2
0.9 V 2 Ω 0.9 V 2 Ω