SBOSAA5B April   2022  – September 2022 OPA2675

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Family Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: Full Bias and Offline Mode VS = ±6 V
    6. 7.6  Electrical Characteristics: 75% Bias Mode VS = ±6 V
    7. 7.7  Electrical Characteristics: 50% Bias Mode VS = ±6 V
    8. 7.8  Electrical Characteristics: DIfferential Output  VS = 12 V
    9. 7.9  Electrical Characteristics: VS = 5 V
    10. 7.10 Typical Characteristics: VS = ±6 V, Full Bias
    11. 7.11 Typical Characteristics: VS = ±6 V Differential, Full Bias
    12. 7.12 Typical Characteristics: VS = ±6 V, 75% Bias
    13. 7.13 Typical Characteristics: VS = ±6 V, 50% Bias
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Operating Suggestions
        1. 8.3.1.1 Setting Resistor Values to Optimize Bandwidth
        2. 8.3.1.2 Output Current and Voltage
        3. 8.3.1.3 Driving Capacitive Loads
        4. 8.3.1.4 Line Driver Headroom Model
        5. 8.3.1.5 Noise Performance
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 High-Speed Active Filters
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Thermal Analysis
    2. 10.2 Input and ESD Protection
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Driving Capacitive Loads

One of the most demanding and yet very common load conditions for an op amp is capacitive loading. The capacitive load is often the input of an analog-to-digital converter (ADC), including additional external capacitance that may be recommended to improve the ADC linearity. A high-speed, high open-loop gain amplifier such as the OPA2675 can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. When the amplifier open-loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin.

Figure 8-6 Driving a Large Capacitive Load Using an Output Series Isolation Resistor

When the primary considerations are frequency response flatness, pulse response fidelity, and distortion, the simplest and most effective solution is to isolate the capacitive load (CL) from the feedback loop by inserting a series isolation resistor (RISO) between the amplifier output and the capacitive load as shown in Figure 8-6. This approach does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. Figure 8-7 and Figure 8-8 shows the Recommended RISO vs CL and the resulting frequency response with the optimized RISO value.

Figure 8-7 Recommended RISO vs Capacitive Load
Figure 8-8 Frequency Response vs Capacitive Load