SBOS925D Data sheet | TI.com

SBOS925D December 2020 – April 2024 OPA2391 , OPA391

PRODMIX

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

DCK|5

Thermal pad, mechanical data (Package|Pins)

Orderable Information

5.9 Typical Characteristics

at T_A = 25°C, V_S = 5.0 V, V_CM = V_S / 2, R_LOAD = 10 kΩ connected to V_S / 2, and C_L = 100 pF (unless otherwise noted)

Figure 5-1 Offset Voltage Distribution

5 units

Figure 5-3 Offset Voltage vs Temperature

30 units, V_S = 5.5 V

Figure 5-5 Offset Voltage vs Common-Mode Voltage

R_L = no load

Figure 5-7 Open-Loop Gain and Phase vs Frequency

V_S = 1.7 V, common-mode voltage referenced to V_S / 2

Figure 5-9 Input Bias Current vs Common-Mode Voltage

V_S = 5.5 V, common-mode voltage referenced to V_S / 2

Figure 5-11 Input Bias Current vs Common-Mode Voltage

Figure 5-13 Negative Input Bias Current Distribution

Figure 5-15 Input Bias Current vs Temperature

Figure 5-17 Output Voltage Swing vs Output Current
(Maximum Supply)

5 units

Figure 5-19 CMRR vs Temperature

Figure 5-21 0.1-Hz to 10-Hz Noise

V_OUT = 1 V_RMS

Figure 5-23 THD+N Ratio vs Frequency

5 units

Figure 5-25 Quiescent Current vs Supply Voltage

5 units

Figure 5-27 Open-Loop Gain vs Temperature

G = +1

Figure 5-29 Small-Signal Overshoot vs Capacitive Load
(10-mV Step)

Figure 5-31 No Phase Reversal

Figure 5-33 Negative Overload Recovery

G = –1

Figure 5-35 Small-Signal Step Response (10-mV Step)

G = –1

Figure 5-37 Large-Signal Step Response (4-V Step)

Figure 5-39 Short-Circuit Current vs Temperature

P_RF = –10 dBm

Figure 5-41 EMIRR vs Frequency

45 units, T_A = –40°C to +125°C

Figure 5-2 Offset Voltage Drift Distribution

5 units

Figure 5-4 Offset Voltage vs Common-Mode Voltage

5 units, V_S = 5.5 V

Figure 5-6 Offset Voltage vs Supply Voltage

Figure 5-8 Closed-Loop Gain and Phase vs Frequency

V_S = 3.3 V, common-mode voltage referenced to V_S / 2

Figure 5-10 Input Bias Current vs Common-Mode Voltage

V_S = 5.5 V, common-mode voltage referenced to V_S / 2

Figure 5-12 Input Bias Current vs Common-Mode Voltage

Figure 5-14 Positive Input Bias Current Distribution

Figure 5-16 Output Voltage Swing vs Output Current
(Maximum Supply)

Figure 5-18 PSRR vs Frequency

5 units

Figure 5-20 PSRR vs Temperature

Figure 5-22 Input Voltage Noise Spectral Density vs Frequency

f = 1 kHz, filter BW = 80 kHz

Figure 5-24 THD+N vs Output Amplitude

5 units

Figure 5-26 Quiescent Current vs Temperature

Figure 5-28 Open-Loop Output Impedance vs Frequency

G = –1

Figure 5-30 Small-Signal Overshoot vs Capacitive Load
(10-mV Step)

Figure 5-32 Positive Overload Recovery

G = +1

Figure 5-34 Small-Signal Step Response (10-mV Step)

G = +1

Figure 5-36 Large-Signal Step Response (4-V Step)

Figure 5-38 Settling Time (1-V Positive Step)

Figure 5-40 Maximum Output Voltage vs Frequency