SBOS803A December   2018  – December 2019 OPA462

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      OPA462 Block Diagram
      2.      Maximum Output Voltage vs Frequency
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics: Table of Graphs
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Status Flag Pin
      2. 7.3.2 Thermal Protection
      3. 7.3.3 Current Limit
      4. 7.3.4 Enable and Disable
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 High DAC Gain Stage for Semiconductor Test Equipment
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Improved Howland Current Pump for Bioimpedance Measurements in Multiparameter Patient Monitors
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Thermally-Enhanced PowerPAD Package
      2. 10.1.2 PowerPAD Integrated Circuit Package Layout Guidelines
      3. 10.1.3 Pin Leakage
      4. 10.1.4 Thermal Protection
      5. 10.1.5 Power Dissipation
      6. 10.1.6 Heat Dissipation
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 TINA-TI™ (Free Software Download)
        2. 11.1.1.2 TI Precision Designs
        3. 11.1.1.3 WEBENCH Filter Designer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Typical Characteristics: Table of Graphs

Table 1. Table of Graphs

DESCRIPTION FIGURE
Offset Voltage Production Distribution at 25°C Figure 1
Offset Voltage Distribution at 85°C Figure 2
Offset Voltage Distribution at -40°C Figure 3
Offset Voltage Drift Distribution from -40°C to 85°C Figure 4
Offset Voltage vs Temperature Figure 5
Offset Voltage Warmup Figure 6
Offset Voltage vs Common-Mode Voltage (Low Vcm) Figure 7
Offset Voltage vs Common-Mode Voltage (High Vcm) Figure 8
Offset Voltage vs Power Supply (Low Supply) Figure 9
Offset Voltage vs Power Supply (High Supply) Figure 10
Offset Voltage vs Output Voltage (Low Output) Figure 11
Offset Voltage vs Output Voltage (High Output) Figure 12
CMRR vs Temperature Figure 13
CMRR vs Frequency Figure 14
PSRR vs Temperature Figure 15
PSRR vs Frequency Figure 16
EMIRR vs Frequency Figure 17
No Phase Reversal Figure 18
Input Bias Current Production Distribution at 25℃ Figure 19
IB vs Temperature Figure 20
IB vs Common-Mode Voltage Figure 21
Enable Response Figure 22
Current Limit Response Figure 23
Open-Loop Gain vs Temperature Figure 24
Open-Loop Gain vs Output Voltage Figure 25
Open-Loop Gain and Phase vs Frequency Figure 26
Open-Loop Output Impedance vs Frequency Figure 27
Closed-Loop Gain vs Frequency Figure 28
Maximum Output Voltage vs Frequency Figure 29
Positive Output Voltage vs Output Current Figure 30
Negative Output Voltage vs Output Current Figure 31
Short-Circuit Current vs Temperature Figure 32
Negative Overload Recovery Figure 33
Positive Overload Recovery Figure 34
Settling Time Figure 35
Phase Margin vs Capacitive Load Figure 36
Small-Signal Overshoot vs Capacitive Load (G = –1) Figure 37
Small-Signal Overshoot vs Capacitive Load (G = +1) Figure 38
Small-Signal Step Response (G = –1) Figure 39
Small-Signal Step Response (G = +1) Figure 40
Large-Signal Step Response (G = –1) Figure 41
Large-Signal Step Response (G = +1) Figure 42
Slew Rate vs Output Step Size Figure 43
Slew Rate vs Supply Voltage (Inverting) Figure 44
Slew Rate vs Supply Voltage (Noninverting) Figure 45
THD+N Ratio vs Frequency (G = 10) Figure 46
THD+N Ratio vs Frequency (G = 20) Figure 47
THD+N Ratio vs Output Amplitude (G = 10) Figure 48
THD+N Ratio vs Output Amplitude (G = 20) Figure 49
0.1-Hz to 10-Hz Noise Figure 50
Input Voltage Noise Spectral Density Figure 51
Current Noise Density Figure 52
Quiescent Current Production Distribution at 25℃ Figure 53
Quiescent Current vs Supply Voltage Figure 54
Quiescent Current vs Temperature Figure 55
Status Flag Voltage vs Temperature Figure 56
Quiescent Current vs Enable Voltage Figure 57
Enable Current vs Enable Voltage Figure 58
Status Flag Current vs Voltage Figure 59