SLOS713I January   2011  – August 2016 OPA2835 , OPA835

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. OPA835-Related Devices
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information: OPA835
    5. 7.5 Thermal Information: OPA2835
    6. 7.6 Electrical Characteristics: VS = 2.7 V
    7. 7.7 Electrical Characteristics: VS = 5 V
    8. 7.8 Typical Characteristics: VS = 2.7 V
    9. 7.9 Typical Characteristics: VS = 5 V
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Common-Mode Voltage Range
      2. 8.3.2 Output Voltage Range
      3. 8.3.3 Power-Down Operation
      4. 8.3.4 Low-Power Applications and the Effects of Resistor Values on Bandwidth
      5. 8.3.5 Driving Capacitive Loads
    4. 8.4 Device Functional Modes
      1. 8.4.1 Split-Supply Operation (±1.25 V to ±2.75 V)
      2. 8.4.2 Single-Supply Operation (2.5 V to 5.5 V)
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1  Noninverting Amplifier
      2. 9.1.2  Inverting Amplifier
      3. 9.1.3  Instrumentation Amplifier
      4. 9.1.4  Attenuators
      5. 9.1.5  Single-Ended to Differential Amplifier
      6. 9.1.6  Differential to Single-Ended Amplifier
      7. 9.1.7  Differential-to-Differential Amplifier
      8. 9.1.8  Gain Setting With OPA835 RUN Integrated Resistors
      9. 9.1.9  Pulse Application With Single-Supply
      10. 9.1.10 ADC Driver Performance
    2. 9.2 Typical Application
      1. 9.2.1 Audio Frequency Performance
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Active Filters
        1. 9.2.2.1 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
      2. 12.2.2 Related Links
      3. 12.2.3 Receiving Notification of Documentation Updates
      4. 12.2.4 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.1.1 Noninverting Amplifier

The OPA835 and OPA2835 devices can be used as noninverting amplifiers with signal input to the noninverting input, VIN+. A basic block diagram of the circuit is shown in Figure 53.

If VIN = VREF + VSIG, the amplifier output may be calculated according to Equation 1.

Equation 1. OPA835 OPA2835 EQ1_vout_los713.gif

The signal gain of the circuit is set by OPA835 OPA2835 Iline1_G_los713.gif, and VREF provides a reference around which the input and output signals swing. Output signals are in-phase with the input signals.

The OPA835 and OPA2835 devices are designed for the nominal value of RF to be 2 kΩ in gains other than +1. This gives excellent distortion performance, maximum bandwidth, best flatness, and best pulse response. RF = 2 kΩ must be used as a default unless other design goals require changing to other values. All test circuits used to collect data for this data sheet had RF = 2 kΩ for all gains other than +1. A gain of +1 is a special case where RF is shorted and RG is left open.

9.1.2 Inverting Amplifier

The OPA835 and OPA2835 devices can be used as inverting amplifiers with signal input to the inverting input, VIN–, through the gain-setting resistor RG. A basic block diagram of the circuit is shown in Figure 54.

If VIN = VREF + VSIG, the output of the amplifier may be calculated according to Equation 2.

Equation 2. OPA835 OPA2835 EQ2_vout2_los713.gif

The signal gain of the circuit OPA835 OPA2835 Iline2_G2_los713.gif and VREF provides a reference point around which the input and output signals swing. Output signals are 180˚ out-of-phase with the input signals. The nominal value of RF must be 2 kΩ for inverting gains.

9.1.3 Instrumentation Amplifier

Figure 64 is an instrumentation amplifier that combines the high input impedance of the differential-to-differential amplifier circuit and the common-mode rejection of the differential-to-single-ended amplifier circuit. This circuit is often used in applications where high input impedance is required (such as taps from a differential line) or in cases where the signal source is a high impedance.

If VIN+ = VCM + VSIG+ and VIN– = VCM + VSIG–, the output of the amplifier may be calculated according to Equation 3.

Equation 3. OPA835 OPA2835 EQ5_vout5_los713.gif

The signal gain of the circuit is OPA835 OPA2835 Iline5_G5_los713.gif. VCM is rejected, and VREF provides a level shift around which the output signal swings. The single-ended output signal is in-phase with the differential input signal.

OPA835 OPA2835 instru_amp_los713.gif Figure 64. Instrumentation Amplifier

Integrated solutions are available, but the OPA835 device provides a much lower-power, high-frequency solution. For best CMRR performance, resistors must be matched. A good rule of thumb is CMRR ≈ the resistor tolerance; so 0.1% tolerance will provide approximately 60-dB CMRR.

9.1.4 Attenuators

The noninverting circuit shown in Figure 53 has a minimum gain of 1. To implement attenuation, a resistor divider can be placed in series with the positive input, and the amplifier set for a gain of 1 by shorting VOUT to VIN– and removing RG. Because the op amp input is high impedance, the resistor divider sets the attenuation.

The inverting circuit of Figure 54 is used as an attenuator by making RG larger than RF. The attenuation is the resistor ratio. For example, a 10:1 attenuator can be implemented with RF = 2 kΩ and RG = 20 kΩ.

9.1.5 Single-Ended to Differential Amplifier

Figure 65 shows an amplifier circuit that converts single-ended signals to differential signals and provides gain and level shifting. This circuit can convert signals to differential in applications such as driving Cat5 cabling or driving differential-input SAR and ΔΣ ADCs.

By setting VIN = VREF + VSIG, then the output of the amplifier may be calculated according to Equation 4.

Equation 4. OPA835 OPA2835 eq_single_ended_los712.gif

The differential-signal gain of the circuit is 2 × G, and VREF provides a reference around which the output signal swings. The differential output signal is in-phase with the single-ended input signal.

OPA835 OPA2835 single_ended_to_diff_los713.gif Figure 65. Single-Ended to Differential Amplifier

Line termination on the output can be accomplished with resistors RO. The differential impedance seen from the line will be 2 × RO. For example, if 100-Ω Cat5 cable is used with double termination, the amplifier is typically set for a differential gain of 2 V/V (6 dB) with RF = 0 Ω (short) RG = ∞Ω (open), 2R = 2 kΩ, R1 = 0 Ω, R = 1 kΩ to balance the input bias currents, and RO = 49.9 Ω for output line termination. This configuration is shown in Figure 66.

For driving a differential-input ADC the situation is similar, but the output resistors, RO, are selected with a capacitor across the ADC input for optimum filtering and settling-time performance.

OPA835 OPA2835 single_ended_to_diff_gain_los713.gif Figure 66. Cat5 Line Driver With Gain = 2 V/V (6 dB)

9.1.6 Differential to Single-Ended Amplifier

Figure 67 shows a differential amplifier that converts differential signals to single-ended and provides gain (or attenuation) and level shifting. This circuit can be used in applications like a line receiver for converting a differential signal from a Cat5 cable to a single-ended signal.

If VIN+ = VCM + VSIG+ and VIN– = VCM + VSIG–, then the output of the amplifier may be calculated according to Equation 5.

Equation 5. OPA835 OPA2835 EQ3_vout3_los713.gif

The signal gain of the circuit is OPA835 OPA2835 Iline3_G3_los713.gif, VCM is rejected, and VREF provides a level shift around which the output signal swings. The single-ended output signal is in-phase with the differential input signal.

OPA835 OPA2835 dif_sng_amp_los713.gif Figure 67. Differential to Single-Ended Amplifier

Line termination can be accomplished by adding a shunt resistor across the VIN+ and VIN- inputs. The differential impedance is the shunt resistance in parallel with the input impedance of the amplifier circuit, which is usually much higher. For low gain and low line impedance, the resistor value to add is approximately the impedance of the line. For example, if a 100-Ω Cat5 cable is used with a gain of 1 amplifier and RF = RG = 2 kΩ, adding a 100-Ω shunt across the input will give a differential impedance of 99 Ω, which is adequate for most applications.

For best CMRR performance, resistors must be matched. Assuming CMRR ≈ the resistor tolerance, a 0.1% tolerance will provide about 60-dB CMRR.

9.1.7 Differential-to-Differential Amplifier

Figure 68 shows a differential amplifier that is used to amplify differential signals. This circuit has high input impedance and is used in differential line driver applications where the signal source is a high-impedance driver (for example, a differential DAC) that must drive a line.

If the user sets VIN± = VCM + VSIG±, then the output of the amplifier may be calculated according to Equation 6.

Equation 6. OPA835 OPA2835 EQ4_vout4_los713.gif

The signal gain of the circuit is OPA835 OPA2835 Iline4_G4_los713.gif, and VCM passes with unity gain. The amplifier combines two noninverting amplifiers into one differential amplifier that shares the RG resistor, which makes RG effectively ½ its value when calculating the gain. The output signals are in-phase with the input signals.

OPA835 OPA2835 dif_dif_amp_los713.gif Figure 68. Differential-to-Differential Amplifier

9.1.8 Gain Setting With OPA835 RUN Integrated Resistors

The OPA835 RUN package option includes integrated gain-setting resistors for the smallest possible footprint on a printed circuit board (≈ 2.00 mm x 2.00 mm). By adding circuit traces on the PCB, gains of +1, –1, –1.33, +2, +2.33, -3, +4, –4, +5, –5.33, +6.33, –7, +8 and inverting attenuations of –0.1429, –0.1875, –0.25, –0.33, –0.75 can be achieved.

Figure 69 shows a simplified view of how the OPA835IRUN integrated gain-setting network is implemented. Table 3 lists the required pin connections for various noninverting and inverting gains (reference Figure 53 and Figure 54). Table 4 lists the required pin connections for various attenuations using the inverting-amplifier architecture (reference Figure 54). Due to ESD protection devices being used on all pins, the absolute maximum and minimum input voltage range, VS– – 0.7 V to VS+ + 0.7 V, applies to the gain-setting resistors, and so attenuation of large input voltages will require external resistors to implement.

The gain-setting resistors are laser trimmed to 1% tolerance with nominal values of 2.4 kΩ, 1.8 kΩ, and 600 Ω. The gain-setting resistors have excellent temperature coefficient, and gain tracking is superior to using external gain-setting resistors. The 800-Ω resistor and 1.25-pF capacitor in parallel with the 2.4-kΩ gain-setting resistor provide compensation for best stability and pulse response.

OPA835 OPA2835 OPA836IRUN_gain_los713.gif Figure 69. OPA835IRUN Gain-Setting Network

Table 3. Gain Settings

NONINVERTING GAIN
(Figure 53)
INVERTING GAIN
(Figure 54)
SHORT PINS SHORT PINS SHORT PINS SHORT PINS
1 V/V (0 dB) 1 to 9
2 V/V (6.02 dB) –1 V/V (0 dB) 1 to 9 2 to 8 6 to GND
2.33 V/V (7.36 dB) –1.33 V/V (2.5 dB) 1 to 9 2 to 8 7 to GND
4 V/V (12.04 dB) –3 V/V (9.54 dB) 1 to 8 2 to 7 6 to GND
5 V/V (13.98 dB) –4 V/V (12.04 dB) 1 to 9 2 to 7 or 8 7 to 8 6 to GND
6.33 V/V (16.03 dB) –5.33 V/V (14.54 dB) 1 to 9 2 to 6 or 8 6 to 8 7 to GND
8 V/V (18.06 dB) –7 V/V (16.90 dB) 1 to 9 2 to 7 6 to GND

Table 4. Attenuator Settings

INVERTING GAIN
(Figure 54)
SHORT PINS SHORT PINS SHORT PINS SHORT PINS
–0.75 V/V (–2.5 dB) 1 to 7 2 to 8 9 to GND
–0.333 V/V (–9.54 dB) 1 to 6 2 to 7 8 to GND
–0.25 V/V (–12.04 dB) 1 to 6 2 to 7 or 8 7 to 8 9 to GND
–0.1875 V/V (–14.54 dB) 1 to 7 2 to 6 or 8 6 to 8 9 to GND
–0.1429 V/V (–16.90 dB) 1 to 6 2 to 7 9 to GND

9.1.9 Pulse Application With Single-Supply

For pulsed applications where the signal is at ground and pulses to a positive or negative voltage, the circuit bias-voltage considerations differ from those in an application with a signal that swings symmetrically about a reference point.Figure 70 shows a circuit where the signal is at ground (0 V) and pulses to a positive value.

OPA835 OPA2835 Ninv_sply_pulse_los1713.gif Figure 70. Noninverting Single Supply With Pulse

If the input signal pulses negative from ground, an inverting amplifier is more appropriate, as shown in Figure 71. A key consideration in noninverting and inverting cases is that the input and output voltages are kept within the limits of the amplifier. Because the VICR of the OPA835 device includes the negative supply rail, the OPA835 op amp is well-suited for this application.

OPA835 OPA2835 inv_sply_pulse_los713.gif Figure 71. Inverting Single Supply With Pulse

9.1.10 ADC Driver Performance

The OPA835 device provides excellent performance when driving high-performance delta-sigma (ΔΣ) and successive-approximation-register (SAR) ADCs in low-power audio and industrial applications.

To show achievable performance, the OPA835 device is tested as the drive amplifier for the ADS8326 device. The ADS8326 device is a 16-bit, micro power, SAR ADC with pseudodifferential inputs and sample rates up to
250 kSPS. The device offers excellent noise and distortion performance in a small 8-pin SOIC or VSSOP (MSOP) package. Low power and small size make the ADS8326 and OPA835 devices an ideal solution for portable and battery-operated systems, remote data-acquisition modules, simultaneous multichannel systems, and isolated data acquisition.

With the circuit shown in Figure 72 to test the performance, Figure 73 shows the spectral performance with a 10-kHz input frequency. The tabulated AC results are in Table 5.

OPA835 OPA2835 tst_cir_los713.gif Figure 72. OPA835 and ADS8326 Test Circuit
OPA835 OPA2835 FFT_los713.gif Figure 73. ADS8326 and OPA835 10-kHz FFT

Table 5. AC Analysis

TONE (Hz) SIGNAL (dBFS) SNR (dBc) THD (dBc) SINAD (dBc) SFDR (dBc)
10k –0.85 81.9 –87.5 80.8 89.9

9.2 Typical Application

9.2.1 Audio Frequency Performance

The OPA835 and OPA2835 devices provide excellent audio performance with low quiescent power. To show performance in the audio band, an audio analyzer from Audio Precision (2700 series) tests THD+N and FFT at 1 VRMS output voltage.

Figure 74 shows the test circuit used for the audio-frequency performance application.

OPA835 OPA2835 AP_tst_cir_los713.gif
The 100-pF capacitor to ground on the input helped to decouple noise pick up in the lab and improved noise performance.
Figure 74. OPA835 Audio Precision Analyzer Test Circuit

9.2.1.1 Design Requirements

Design a low distortion, single-ended input to single-ended output audio amplifier using the OPA835 device. The 2700 series audio analyzer from Audio Precision is the signal source and the measurement system.

Table 6. Design Requirements

CONFIGURATION INPUT
EXCITATION
PERFORMANCE
TARGET
RLOAD
OPA835 Unity Gain Config. 1 KHz Tone Frequency > 110 dBc SFDR 300 Ω and
100 KΩ

9.2.1.2 Detailed Design Procedure

The OPA835 device is tested in this application in a unity-gain buffer configuration. A buffer configuration is selected as the configuration maximizes the loop gain of the amplifier configuration. At higher closed-loop gains, the loop gain of the circuit reduces, which results in degraded harmonic distortion. The relationship between distortion and closed loop gain at a fixed input frequency can be seen in Figure 36 in Typical Characteristics: VS = 5 V. The test was performed under varying output-load conditions using a resistive load of 300 Ω and 100 KΩ. Figure 34 shows the distortion performance of the amplifier versus the output resistive load. Output loading, output swing, and closed-loop gain play a key role in determining the distortion performance of the amplifier.

NOTE

The 100-pF capacitor to ground on the input helped to decouple noise pickup in the lab and improved noise performance.

The Audio Precision was configured as a single-ended output in this application circuit. In applications where a differential output is available, the OPA835 device can be configured as a differential to single-ended amplifier as shown in Figure 67. Power supply bypassing is critical to reject noise from the power supplies. A 2.2-μF power-supply decoupling capacitor must be placed within two inches of the device and can be shared with other op amps on the same board. A 0.1-μF decoupling capacitor must be placed as close to the power supply pins as possible, preferably within 0.1 inch. For split supply, a capacitor is required for both supplies. A 0.1-µF capacitor placed directly between the supplies is also beneficial for improving system noise performance. If the output load is heavy, from 16 Ω to 32 Ω, amplifier performance could begin to degrade. To drive such heavy loads, both channels of the OPA2835 device can be paralleled with the outputs isolated with 1-Ω resistors to reduce the loading effects.

9.2.1.3 Application Curves

A 10-Ω series resistor can be inserted between the capacitor and the noninverting pin to isolate the capacitance.

Figure 75 shows the THD+N performance with 100-kΩ and 300-Ω loads, and with no weighting and A-weighting. With no weighting, the THD+N performance is dominated by the noise for both loads. A-weighting provides filtering that improves the noise so a larger difference can be seen between the loads due to more distortion with RL = 300 Ω.

Figure 76 and Figure 77 show FFT output with a 1-kHz tone and 100-kΩ and 300-Ω loads. To show relative performance of the device versus the test set, one channel has the OPA835 device in-line between generator output and analyzer input, and the other channel is in “Gen Mon” loopback mode, which internally connects the signal generator to the analyzer input. With 100-kΩ load (see Figure 76), the curves are indistinguishable from each other except for noise, which means the OPA835 device cannot be directly measured. With a 300-Ω load as shown in Figure 77, the main difference between the curves is the OPA835 device due to the higher even-order harmonics. The test-set performance masks the odd-order harmonics.

OPA835 OPA2835 app_tc3_5v_los713.gif Figure 75. OPA835 1 VRMS 20 Hz to 80 kHz THD+N
OPA835 OPA2835 app_FFT2_los713.gif Figure 77. OPA835 and AP Gen Mon 1kHz FFT Plot;
VOUT = 1 VRMS, RL = 300 Ω
OPA835 OPA2835 app_FFT1_los713.gif Figure 76. OPA835 and AP Gen Mon 1-kHz FFT Plot;
VOUT = 1 VRMS, RL = 100 kΩ

9.2.2 Active Filters

The OPA835 and OPA2835 devices are good choices for active filters. Figure 79 and Figure 78 show MFB and Sallen-Key circuits designed using the WEBENCH® Filter Designer to implement second-order low-pass Butterworth filter circuits. Figure 80 shows the frequency response.

Other MFB and Sallen-Key filter circuits display similar performance. The main difference is the MFB is an inverting amplifier in the pass band and the Sallen-Key is noninverting. The primary advantage for each is the Sallen-Key in unity gain has no resistor gain error term, and thus no sensitivity to gain error, while the MFB has better attenuation properties beyond the bandwidth of the op amp.

OPA835 OPA2835 MFB_cir_los713.gif Figure 78. MFB 100-kHz Second-Order Low-Pass Butterworth Filter Circuit
OPA835 OPA2835 sllen_key_los713.gif Figure 79. Sallen-Key 100-kHz Second-Order Low-Pass Butterworth Filter Circuit

9.2.2.1 Application Curve

OPA835 OPA2835 app_tc2_5v_los713.gif Figure 80. MFB and Sallen-Key Second-Order Low-Pass Butterworth Filter Response