SBOS929A December   2018  – December 2021 OPT3004

PRODMIX  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Human Eye Matching
      2. 8.3.2 Automatic Full-Scale Range Setting
      3. 8.3.3 Interrupt Operation, INT Pin, and Interrupt Reporting Mechanisms
      4. 8.3.4 I2C Bus Overview
        1. 8.3.4.1 Serial Bus Address
        2. 8.3.4.2 Serial Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1 Automatic Full-Scale Setting Mode
      2. 8.4.2 Interrupt Reporting Mechanism Modes
        1. 8.4.2.1 Latched Window-Style Comparison Mode
        2. 8.4.2.2 Transparent Hysteresis-Style Comparison Mode
        3. 8.4.2.3 End-of-Conversion Mode
        4. 8.4.2.4 End-of-Conversion and Transparent Hysteresis-Style Comparison Mode
    5. 8.5 Programming
      1. 8.5.1 Writing and Reading
        1. 8.5.1.1 High-Speed I2C Mode
        2. 8.5.1.2 General-Call Reset Command
        3. 8.5.1.3 SMBus Alert Response
    6. 8.6 Register Maps
      1. 8.6.1 Internal Registers
      2. 8.6.2 Register Descriptions
        1. 8.6.2.1 Result Register (offset = 00h)
        2. 8.6.2.2 Configuration Register (offset = 01h) [reset = C810h]
        3. 8.6.2.3 Low-Limit Register (offset = 02h) [reset = C0000h]
        4. 8.6.2.4 High-Limit Register (offset = 03h) [reset = BFFFh]
        5. 8.6.2.5 Manufacturer ID Register (offset = 7Eh) [reset = 5449h]
        6. 8.6.2.6 Device ID Register (offset = 7Fh) [reset = 3001h]
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Electrical Interface
      2. 9.1.2 Optical Interface
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Optomechanical Design
        2. 9.2.2.2 Dark Window Selection and Compensation
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
  10. 10Power-Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Soldering and Handling Recommendations
    4. 11.4 DNP (S-PDSO-N6) Mechanical Drawings
    5. 11.5 DTS (SOT-5X3) Mechanical Drawings
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Writing and Reading

Accessing a specific register on the OPT3004 is accomplished by writing the appropriate register address during the I2C transaction sequence. Refer to Table 8-6 for a complete list of registers and their corresponding register addresses. The value for the register address (as shown in Figure 8-1) is the first byte transferred after the target address byte with the R/W bit low.

GUID-4C189A0B-FA1E-407A-AA4F-C42AF9597210-low.gif
The value of the target address byte is determined by the ADDR pin setting; see Table 8-1.
Figure 8-1 Setting the I2C Register Address

Writing to a register begins with the first byte transmitted by the controller. This byte is the target address with the R/W bit low. The OPT3004 then acknowledges receipt of a valid address. The next byte transmitted by the controller is the address of the register that data are to be written to. The next two bytes are written to the register addressed by the register address. The OPT3004 acknowledges receipt of each data byte. The controller may terminate the data transfer by generating a start or stop condition.

When reading from the OPT3004, the last value stored in the register address by a write operation determines which register is read during a read operation. To change the register address for a read operation, a new partial I2C write transaction must be initiated. This partial write is accomplished by issuing a target address byte with the R/W bit low, followed by the register address byte and a stop command. The controller then generates a start condition and sends the target address byte with the R/W bit high to initiate the read command. The next byte is transmitted by the target and is the most significant byte of the register indicated by the register address. This byte is followed by an acknowledge from the controller; then the target transmits the least significant byte. The controller acknowledges receipt of the data byte. The controller may terminate the data transfer by generating a not-acknowledge after receiving any data byte, or by generating a start or stop condition. If repeated reads from the same register are desired, continually sending the register address bytes is not necessary; the OPT3004 retains the register address until that number is changed by the next write operation.

Figure 8-2 and Figure 8-3 show the write and read operation timing diagrams, respectively. Note that register bytes are sent most significant byte first, followed by the least significant byte.

GUID-D63D0E48-6449-4839-9CF8-61D746E485F5-low.gif
The value of the target address byte is determined by the setting of the ADDR pin; see Table 8-1.
Figure 8-2 I2C Write Example
GUID-8C30654F-3EBB-4E45-9297-EB0080D7E18E-low.gif
The value of the target address byte is determined by the ADDR pin setting; see Table 8-1.
An ACK by the controller can also be sent.
Figure 8-3 I2C Read Example