SBAS703A June   2015  – June 2015 OPT9221

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 DDR2 Interface
      2. 7.3.2 I2C Master Interface
      3. 7.3.3 Timing Coordinator
        1. 7.3.3.1 Basic Frame Structure
        2. 7.3.3.2 Frame Rate Control and Sub Frames
        3. 7.3.3.3 Input Clock Generation
        4. 7.3.3.4 Sensor Addressing Engine
          1. 7.3.3.4.1 Region of Interest (ROI)
          2. 7.3.3.4.2 Readout Sequence
        5. 7.3.3.5 Integration Time
          1. 7.3.3.5.1 High Dynamic Range Functionality
        6. 7.3.3.6 Modulation Clock Generator
          1. 7.3.3.6.1 Sensor Output Signals
      4. 7.3.4 Output Interface
        1. 7.3.4.1 Output Data Format
          1. 7.3.4.1.1 4-Byte Mode (default)
          2. 7.3.4.1.2 2-Byte Mode
          3. 7.3.4.1.3 Register Controls
        2. 7.3.4.2 Frame Fragmentation
        3. 7.3.4.3 Data Output Waveforms
          1. 7.3.4.3.1 8-Lane Mode - DVP
          2. 7.3.4.3.2 8-Lane Mode - Generic Parallel Interface
          3. 7.3.4.3.3 4-Lane Mode - SSI
          4. 7.3.4.3.4 1-Lane Mode - SSI
          5. 7.3.4.3.5 Register Controls
      5. 7.3.5 Modulation Frequency
      6. 7.3.6 LVDS Receiver and Deserializer
      7. 7.3.7 Depth Engine
        1. 7.3.7.1 Phase Data
        2. 7.3.7.2 De-Aliasing
          1. 7.3.7.2.1 Procedure for Enabling the De-Aliasing Mode
          2. 7.3.7.2.2 Procedure for Disabling the De-Aliasing Mode
          3. 7.3.7.2.3 Setting the De-Aliasing Coefficients
          4. 7.3.7.2.4 Scaling of Phase
          5. 7.3.7.2.5 LSBs in the De-Aliased Phase
        3. 7.3.7.3 Binning
        4. 7.3.7.4 Spatial Filter
        5. 7.3.7.5 Auxiliary Depth Data
      8. 7.3.8 Calibration
        1. 7.3.8.1 Phase Offset Correction
        2. 7.3.8.2 Illumination Path Delay Correction Using Feedback
        3. 7.3.8.3 Phase Non-Linearity Correction
    4. 7.4 Device Functional Modes
      1. 7.4.1 Standby and Low-Power Modes
    5. 7.5 Programming
      1. 7.5.1 Boot Sequence
        1. 7.5.1.1 Configuration
          1. 7.5.1.1.1 Master Serial Configuration
          2. 7.5.1.1.2 Slave Serial Configuration (SS mode)
          3. 7.5.1.1.3 Slave Parallel Configuration (SP mode)
          4. 7.5.1.1.4 Slave Parallel and Serial Timing
      2. 7.5.2 Slave I2C Interface
    6. 7.6 Register Maps
      1. 7.6.1 Serial Interface Register Map
      2. 7.6.2 Register Descriptions
        1. 7.6.2.1  Register 0h (offset = 0h) [reset = 0h]
        2. 7.6.2.2  Register 1h (offset = 1h) [reset = 1XXh]
        3. 7.6.2.3  Register 2h (offset = 2h) [reset = 100C81h]
        4. 7.6.2.4  Register 3h (offset = 3h) [reset = 100000h]
        5. 7.6.2.5  Register 4h (offset = 4h) [reset = 0h]
        6. 7.6.2.6  Register 5h (offset = 5h) [reset = 7FFFh]
        7. 7.6.2.7  Register 6h (offset = 6h) [reset = 0h]
        8. 7.6.2.8  Register 7h (offset = 7h) [reset = 8001h]
        9. 7.6.2.9  Register 8h (offset = 8h) [reset = 0h]
        10. 7.6.2.10 Register 9h (offset = 9h) [reset = 0h]
        11. 7.6.2.11 Register Ah (offset = Ah) [reset = 7FFFh]
        12. 7.6.2.12 Register Bh (offset = Bh) [reset = 0h]
        13. 7.6.2.13 Register Ch (offset = Ch) [reset = 8001h]
        14. 7.6.2.14 Register Dh (offset = Dh) [reset = 0h]
        15. 7.6.2.15 Register Eh (offset = Eh) [reset = 0h]
        16. 7.6.2.16 Register Fh (offset = Fh) [reset = 0h]
        17. 7.6.2.17 Register 10h (offset = 10h) [reset = 0h]
        18. 7.6.2.18 Register 11h (offset = 11h) [reset = 6ED9h]
        19. 7.6.2.19 Register 12h (offset = 12h) [reset = 9127h]
        20. 7.6.2.20 Register 13h (offset = 13h) [reset = 0h]
        21. 7.6.2.21 Register 14h (offset = 14h) [reset = 6ED9h]
        22. 7.6.2.22 Register 15h (offset = 15h) [reset = 9127h]
        23. 7.6.2.23 Register 16h (offset = 16h) [reset = 7FFFh]
        24. 7.6.2.24 Register 17h (offset = 17h) [reset = C000h]
        25. 7.6.2.25 Register 18h (offset = 18h) [reset = C000h]
        26. 7.6.2.26 Register 19h (offset = 19h) [reset = 7FFFh]
        27. 7.6.2.27 Register 1Ah (offset = 1Ah) [reset = C000h]
        28. 7.6.2.28 Register 1Bh (offset = 1Bh) [reset = C000h]
        29. 7.6.2.29 Register 1Fh (offset = 1Fh) [reset = 54321h]
        30. 7.6.2.30 Register 25h (offset = 25h) [reset = 80001h]
        31. 7.6.2.31 Register 27h (offset = 27h) [reset = 2000h]
        32. 7.6.2.32 Register 28h (offset = 28h) [reset = 0h]
        33. 7.6.2.33 Register 29h (offset = 29h) [reset = 304000h]
        34. 7.6.2.34 Register 2Eh (offset = 2Eh) [reset = 871h]
        35. 7.6.2.35 Register 2Fh (offset = 2Fh) [reset = 3C0001h]
        36. 7.6.2.36 Register 30h (offset = 30h) [reset = 500001h]
        37. 7.6.2.37 Register 31h (offset = 31h) [reset = 1802h]
        38. 7.6.2.38 Register 33h (offset = 33h) [reset = 30h]
        39. 7.6.2.39 Register 35h (offset = 35h) [reset = 800000h]
        40. 7.6.2.40 Register 36h (offset = 36h) [reset = 0h]
        41. 7.6.2.41 Register 37h (offset = 37h) [reset = 0h]
        42. 7.6.2.42 Register 38h (offset = 38h) [reset = 0h]
        43. 7.6.2.43 Register 39h (offset = 39h) [reset = 0h]
        44. 7.6.2.44 Register 3Ah (offset = 3Ah) [reset = 0h]
        45. 7.6.2.45 Register 3Bh (offset = 3Bh) [reset = 0h]
        46. 7.6.2.46 Register 3Ch (offset = 3Ch) [reset = 4000h]
        47. 7.6.2.47 Register 3Dh (offset = 3Dh) [reset = 0h]
        48. 7.6.2.48 Register 3Eh (offset = 3Eh) [reset = 80h]
        49. 7.6.2.49 Register 3Fh (offset = 3Fh) [reset = Bh]
        50. 7.6.2.50 Register 40h (offset = 40h) [reset = 50455h]
        51. 7.6.2.51 Register 47h (offset = 47h) [reset = 0h]
        52. 7.6.2.52 Register 48h (offset = 48h) [reset = 0h]
        53. 7.6.2.53 Register 4Ch (offset = 4Ch) [reset = 800006h]
        54. 7.6.2.54 Register 4Dh (offset = 4Dh) [reset = 0h]
        55. 7.6.2.55 Register 51h (offset = 51h) [reset = 140000h]
        56. 7.6.2.56 Register 52h (offset = 52h) [reset = 0h]
        57. 7.6.2.57 Register 61h (offset = 61h) [reset = 0h]
        58. 7.6.2.58 Register 62h (offset = 62h) [reset = 0h]
        59. 7.6.2.59 Register 63h (offset = 63h) [reset = 0h]
        60. 7.6.2.60 Register 65h (offset = 65h) [reset = 0h]
        61. 7.6.2.61 Register 66h (offset = 66h) [reset = 0h]
        62. 7.6.2.62 Register 80h (offset = 80h) [reset = 0h]
        63. 7.6.2.63 Register 81h (offset = 81h) [reset = 0h]
        64. 7.6.2.64 Register 82h (offset = 82h) [reset = 0h]
        65. 7.6.2.65 Register 83h (offset = 83h) [reset = 0h]
        66. 7.6.2.66 Register 84h (offset = 84h) [reset = 0h]
        67. 7.6.2.67 Register 85h (offset = 85h) [reset = 0h]
        68. 7.6.2.68 Register 86h (offset = 86h) [reset = 0h]
        69. 7.6.2.69 Register 87h (offset = 87h) [reset = 0h]
        70. 7.6.2.70 Register 88h (offset = 88h) [reset = 0h]
        71. 7.6.2.71 Register 91h (offset = 91h) [reset = 0h]
        72. 7.6.2.72 Register 92h (offset = 92h) [reset = 0h]
        73. 7.6.2.73 Register 93h (offset = 93h) [reset = 0h]
        74. 7.6.2.74 Register 94h (offset = 94h) [reset = 0h]
        75. 7.6.2.75 Register 95h (offset = 95h) [reset = 0h]
        76. 7.6.2.76 Register 96h (offset = 96h) [reset = 0h]
        77. 7.6.2.77 Register 97h (offset = 97h) [reset = 0h]
        78. 7.6.2.78 Register 98h (offset = 98h) [reset = 0h]
        79. 7.6.2.79 Register ABh (offset = ABh) [reset = 0h]
        80. 7.6.2.80 Register ACh (offset = ACh) [reset = 0h]
        81. 7.6.2.81 Register ADh (offset = ADh) [reset = 0h]
        82. 7.6.2.82 Register AEh (offset = AEh) [reset = 0h]
        83. 7.6.2.83 Register AFh (offset = AFh) [reset = 0h]
        84. 7.6.2.84 Register B0h (offset = B0h) [reset = 0h]
        85. 7.6.2.85 Register B1h (offset = B1h) [reset = 5004h]
        86. 7.6.2.86 Register B2h (offset = B2h) [reset = C00h]
        87. 7.6.2.87 Register B3h (offset = B3h) [reset = 800h]
        88. 7.6.2.88 Register B6h (offset = B6h) [reset = 0h]
      3. 7.6.3 Serial Interface Register Map
        1. 7.6.3.1  Register 2h (offset = 2h) [reset = 0h]
        2. 7.6.3.2  Register Ch (offset = Ch) [reset = 100000h]
        3. 7.6.3.3  Register Dh (offset = Dh) [reset = 100000h]
        4. 7.6.3.4  Register Eh (offset = Eh) [reset = 04h]
        5. 7.6.3.5  Register Fh (offset = Fh) [reset = 49Ah]
        6. 7.6.3.6  Register 12h (offset = 12h) [reset = 0h]
        7. 7.6.3.7  Register 1Fh (offset = 1Fh) [reset = EF0000h]
        8. 7.6.3.8  Register 20h (offset = 20h) [reset = 0h]
        9. 7.6.3.9  Register 21h (offset = 21h) [reset = 40009Fh]
        10. 7.6.3.10 Register 22h (offset = 22h) [reset = 12020h]
        11. 7.6.3.11 Register 80h (offset = 80h) [reset = 1h]
        12. 7.6.3.12 Register 81h (offset = 81h) [reset = A0h]
        13. 7.6.3.13 Register 82h (offset = 82h) [reset = 186A0h]
        14. 7.6.3.14 Register 83h (offset = 83h) [reset = 44h]
        15. 7.6.3.15 Register CCh (offset = CCh) [reset = 400003h]
        16. 7.6.3.16 Register D6h (offset = D6h) [reset = 1h]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Up Sequence
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 DDR Placement and Routing
      2. 10.1.2 LVDS Receiver
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

ZVM Package
256-Ball NFBGA
Top View

Pin Functions

PIN I/O I/O STANDARD I/O BANK DESCRIPTION
NAME NO.
BOOT_0 H13 Input 2.5 V – Boot configuration pin 0. Tie to VCC or to GND.
BOOT_1 H12 Input 2.5 V – Boot configuration pin 1. Tie to VCC or to GND.
BOOT_2 G12 Input 2.5 V – Boot configuration pin 2. Tie to VCC or to GND.
CAP_BIT_CLKM M16 Input LVDS VCCIO5 Sensor data bit clk
CAP_BIT_CLKP M15 Input LVDS VCCIO5 Sensor data bit clk
CAP_DATA_DIFF_0M N16 Input LVDS VCCIO5 Sensor differential data ch 0
CAP_DATA_DIFF_0P N15 Input LVDS VCCIO5 Sensor differential data ch 0
CAP_DATA_DIFF_1M K16 Input LVDS VCCIO5 Sensor differential data ch 1
CAP_DATA_DIFF_1P K15 Input LVDS VCCIO5 Sensor differential data ch 1
CAP_DATA_SUM_M J16 Input LVDS VCCIO5 Sensor common mode data
CAP_DATA_SUM_P J15 Input LVDS VCCIO5 Sensor common mode data
CAP_FRM_CLKM P16 Input LVDS VCCIO5 Sensor sample clk
CAP_FRM_CLKP R16 Input LVDS VCCIO5 Sensor sample clk
COMP_MOD_FB E16 Input 3.3 V VCCIO6 Feedback signal from the external illumination modulation feedback comparator.
COMP_MOD_REF F16 Output 3.3 V VCCIO6 Reference modulation signal for measuring external illumination modulation feedback comparator delay.
DDR2_ADDR_0 L11 Output SSTL-18 Class I VCCIO4 DDR address signal 0
DDR2_ADDR_1 L9 Output SSTL-18 Class I VCCIO4 DDR address signal 1
DDR2_ADDR_2 K10 Output SSTL-18 Class I VCCIO4 DDR address signal 2
DDR2_ADDR_3 K9 Output SSTL-18 Class I VCCIO4 DDR address signal 3
DDR2_ADDR_4 M11 Output SSTL-18 Class I VCCIO4 DDR address signal 4
DDR2_ADDR_5 M9 Output SSTL-18 Class I VCCIO4 DDR address signal 5
DDR2_ADDR_6 L10 Output SSTL-18 Class I VCCIO4 DDR address signal 6
DDR2_ADDR_7 T6 Output SSTL-18 Class I VCCIO3 DDR address signal 7
DDR2_ADDR_8 N11 Output SSTL-18 Class I VCCIO4 DDR address signal 8
DDR2_ADDR_9 P9 Output SSTL-18 Class I VCCIO4 DDR address signal 9
DDR2_ADDR_10 N3 Output SSTL-18 Class I VCCIO3 DDR address signal 10
DDR2_ADDR_11 M10 Output SSTL-18 Class I VCCIO4 DDR address signal 11
DDR2_ADDR_12 T5 Output SSTL-18 Class I VCCIO3 DDR address signal 12
DDR2_BA_0 R4 Output SSTL-18 Class I VCCIO3 DDR bank signal
DDR2_BA_1 T4 Output SSTL-18 Class I VCCIO3 DDR bank signal
DDR2_CASZ T11 Output SSTL-18 Class I VCCIO4 DDR CAS
DDR2_CKE T2 Output SSTL-18 Class I VCCIO3 DDR clock enable
DDR2_CLK_0 R14 Output SSTL-18 Class I VCCIO4 DDR clock
DDR2_CLKz_0 P14 Output SSTL-18 Class I VCCIO4 DDR clock
DDR2_CSZ R13 Output SSTL-18 Class I VCCIO4 DDR chip select
DDR2_DM_0 P3 Output SSTL-18 Class I VCCIO3 DDR data mask 0
DDR2_DM_1 M8 Output SSTL-18 Class I VCCIO3 DDR data mask 1
DDR2_DQ_0 L7 Bidir SSTL-18 Class I VCCIO3 DDR data 15
DDR2_DQ_1 N5 Bidir SSTL-18 Class I VCCIO3 DDR data 14
DDR2_DQ_2 R6 Bidir SSTL-18 Class I VCCIO3 DDR data 13
DDR2_DQ_3 N6 Bidir SSTL-18 Class I VCCIO3 DDR data 12
DDR2_DQ_4 R5 Bidir SSTL-18 Class I VCCIO3 DDR data 11
DDR2_DQ_5 R7 Bidir SSTL-18 Class I VCCIO3 DDR data 10
DDR2_DQ_6 R3 Bidir SSTL-18 Class I VCCIO3 DDR data 9
DDR2_DQ_7 L8 Bidir SSTL-18 Class I VCCIO3 DDR data 8
DDR2_DQ_8 R12 Bidir SSTL-18 Class I VCCIO4 DDR data 7
DDR2_DQ_9 N9 Bidir SSTL-18 Class I VCCIO4 DDR data 6
DDR2_DQ_10 R11 Bidir SSTL-18 Class I VCCIO4 DDR data 5
DDR2_DQ_11 R10 Bidir SSTL-18 Class I VCCIO4 DDR data 4
DDR2_DQ_12 P8 Bidir SSTL-18 Class I VCCIO3 DDR data 3
DDR2_DQ_13 T14 Bidir SSTL-18 Class I VCCIO4 DDR data 2
DDR2_DQ_14 N8 Bidir SSTL-18 Class I VCCIO3 DDR data 1
DDR2_DQ_15 T13 Bidir SSTL-18 Class I VCCIO4 DDR data 0
DDR2_DQS_0 M7 Output SSTL-18 Class I VCCIO3 DDR data strobe
DDR2_DQS_1 T7 Output SSTL-18 Class I VCCIO3 DDR data strobe
DDR2_ODT_0 T15 Bidir SSTL-18 Class I VCCIO4 DDR on die termination
DDR2_RASZ T12 Output SSTL-18 Class I VCCIO4 DDR RAS
DDR2_REF_0 T3 Input Analog – DDR reference, tie to 0.9 V
DDR2_REF_1 P6 Input Analog – DDR reference, tie to 0.9 V
DDR2_REF_2 P11 Input Analog – DDR reference, tie to 0.9 V
DDR2_REF_3 N12 Input Analog – DDR reference, tie to 0.9 V
DDR2_WEZ T10 Output SSTL-18 Class I VCCIO4 DDR write enable
DEBUG D1 Bidir 1.8 V VCCIO1 TI proprietary debug port. Pullup by 10 kΩ.
FE L6 Output 1.8 V VCCIO2 Marks the end of a frame
GND B2 Power – – Digital ground
GND B15 Power – – Digital ground
GND C5 Power – – Digital ground
GND C12 Power – – Digital ground
GND D7 Power – – Digital ground
GND D10 Power – – Digital ground
GND E2 Power – – Digital ground
GND E4 Power – – Digital ground
GND E13 Power – – Digital ground
GND F6 Power – – Digital ground
GND F10 Power – – Digital ground
GND G4 Power – – Digital ground
GND G13 Power – – Digital ground
GND H7 Power – – Digital ground
GND H8 Power – – Digital ground
GND H9 Power – – Digital ground
GND H10 Power – – Digital ground
GND H15 Power – – Digital ground
GND H16 Power – – Digital ground
GND J7 Power – – Digital ground
GND J8 Power – – Digital ground
GND J9 Power – – Digital ground
GND J10 Power – – Digital ground
GND J11 Power – – Digital ground
GND K4 Power – – Digital ground
GND K8 Power – – Digital ground
GND K13 Power – – Digital ground
GND M4 Power – – Digital ground
GND M13 Power – – Digital ground
GND N7 Power – – Digital ground
GND N10 Power – – Digital ground
GND P5 Power – – Digital ground
GND P12 Power – – Digital ground
GND R2 Power – – Digital ground
GND R15 Power – – Digital ground
GNDA1 M5 Power – – Analog ground
GNDA2 E12 Power – – Analog ground
GNDA3 E5 Power – – Analog ground
GNDA4 M12 Power – – Analog ground
GPI_0 F9 Input 1.8 V VCCIO7 Sensor general purpose pin
GPI_1 E9 Input 1.8 V VCCIO7 Sensor general purpose pin
GPO_1 B3 Output 1.8 V VCCIO8 General purpose output
GPO_2 A3 Output 1.8 V VCCIO8 General purpose output
GPO_3 A2 Output 1.8 V VCCIO8 General purpose output
GPO_0 A4 Output 1.8 V VCCIO8 General purpose output
HD/BD J2 Output 1.8 V VCCIO2 Indicates the row boundary or block boundary
HD_QD A11 Input 1.8 V VCCIO7 Sensor HD
ILLUM_FB B16 Input 3.3 V VCCIO6 Comparator output feedback to TFC
ILLUM_MOD_FB E15 Input 3.3 V VCCIO6 Illumination modulation signal input. Connect to ILLUM_P/M of the OPT8241 sensor.
ILLUM_REF F13 Output 3.3 V VCCIO6 Comparator reference signal
ILLUM_SW_1 C16 Output 3.3 V VCCIO6 DCDC control signal 1
ILLUM_SW_2 C15 Output 3.3 V VCCIO6 DCDC control signal 2
INT_OUT G2 Output 1.8 V VCCIO1 Interrupt to external host
INT_PMIC G5 Input 1.8 V VCCIO1 Interrupt from PMIC
IO_MOD_REF F15 Output 3.3 V VCCIO6 Reference modulation signal from the TFC for measuring TFC I/O delay
I2C_MAS_SCL D8 Output 1.8 V VCCIO8 I2C master clk
I2C_MAS_SDA C8 Bidir 1.8 V VCCIO8 I2C master data
I2C_SCL_SENSOR D9 Output 1.8 V VCCIO7 Dedicated I2C for sensor - clock
I2C_SDA_SENSOR C9 Bidir 1.8 V VCCIO7 Dedicated I2C for sensor - data
I2C_SLV_SCL F1 Input 1.8 V VCCIO1 I2C slave clk
I2C_SLV_SDA F2 Bidir 1.8 V VCCIO1 I2C slave data
OP_CLK K5 Output 1.8 V VCCIO2 Output data clock
OP_CS K6 Output 1.8 V VCCIO2 Indicates the validity of the data output. Useful for SPI mode.
OP_DATA_0 R1 Output 1.8 V VCCIO2 Output data bit 0
OP_DATA_1 P1 Output 1.8 V VCCIO2 Output data bit 1
OP_DATA_2 P2 Output 1.8 V VCCIO2 Output data bit 2
OP_DATA_3 N1 Output 1.8 V VCCIO2 Output data bit 3
OP_DATA_4 N2 Output 1.8 V VCCIO2 Output data bit 4
OP_DATA_5 L1 Output 1.8 V VCCIO2 Output data bit 5
OP_DATA_6 L2 Output 1.8 V VCCIO2 Output data bit 6
OP_DATA_7 L4 Output 1.8 V VCCIO2 Output data bit 7
OVERFLOW L3 Input 1.8 V VCCIO2 Used to indicate failure in flow control.
PHASE_AUX K2 Output 1.8 V VCCIO2 Indicates the type of data on the output bus.
READY M1 Input 1.8 V VCCIO2 Used to achieve flow control of the output data.
RESETZ C2 Input 1.8 V VCCIO1 Global reset for the TFC
RSVD A6 Bidir 1.8 V VCCIO8 Reserved. Leave unconnected.
RSVD B4 Bidir 3.3 V VCCIO6 Leave unconnected
RSVD B5 Bidir 1.8 V VCCIO8 Reserved. Leave unconnected.
RSVD B6 Bidir 1.8 V VCCIO8 Reserved. Leave unconnected.
RSVD B10 Bidir 1.8 V VCCIO7 Leave unconnected
RSVD B11 Bidir 1.8 V VCCIO7 Leave unconnected
RSVD B12 Bidir 1.8 V VCCIO7 Leave unconnected
RSVD B13 Bidir 1.8 V VCCIO7 Leave unconnected
RSVD C3 Bidir 1.8 V VCCIO8 Leave unconnected
RSVD C6 Bidir 1.8 V VCCIO8 Reserved. Leave unconnected.
RSVD C11 Bidir 1.8 V VCCIO7 Leave unconnected
RSVD C14 Bidir 1.8 V VCCIO7 Leave unconnected
RSVD D3 Bidir 1.8 V VCCIO8 Reserved. Leave unconnected.
RSVD D5 Bidir 1.8 V VCCIO8 Reserved. Leave unconnected.
RSVD D6 Bidir 1.8 V VCCIO8 Reserved. Leave unconnected.
RSVD D11 Bidir 1.8 V VCCIO7 Leave unconnected
RSVD D12 Bidir 1.8 V VCCIO7 Leave unconnected
RSVD D15 Bidir 3.3 V VCCIO6 Leave unconnected
RSVD D16 Bidir 3.3 V VCCIO6 Leave unconnected
RSVD E10 Bidir 1.8 V VCCIO7 Leave unconnected
RSVD E11 Bidir 1.8 V VCCIO7 Leave unconnected
RSVD F3 Bidir 1.8 V VCCIO1 Leave unconnected
RSVD F14 Bidir 3.3 V VCCIO6 Leave unconnected
RSVD G1 Bidir 1.8 V VCCIO1 Leave unconnected
RSVD G11 Bidir 3.3 V VCCIO6 Leave unconnected
RSVD G15 Bidir 3.3 V VCCIO6 Leave unconnected
RSVD J1 Output 1.8 V VCCIO2 Reserved
RSVD J12 Bidir 2.5 V VCCIO5 Leave unconnected
RSVD J13 Bidir 2.5 V VCCIO5 Leave unconnected
RSVD J14 Bidir 2.5 V VCCIO5 Leave unconnected
RSVD K12 Bidir 2.5 V VCCIO5 Leave unconnected
RSVD L13 Bidir 2.5 V VCCIO5 Leave unconnected
RSVD L16 Bidir 2.5 V VCCIO5 Leave unconnected
RSVD M6 Bidir 1.8 V VCCIO3 Leave unconnected
RSVD N14 Bidir 2.5 V VCCIO5 Leave unconnected
RSVD P15 Bidir 2.5 V VCCIO5 Leave unconnected
RSVD_IN A8 Input 1.8 V VCCIO8 Tie to GND
RSVD_IN A9 Input 1.8 V VCCIO7 Tie to GND
RSVD_IN B8 Input 1.8 V VCCIO8 Tie to GND
RSVD_IN B9 Input 1.8 V VCCIO7 Tie to GND
RSVD_IN L14 Input Analog VCCIO5 Tie to 2.5 V
RSVD_IN L15 Input Analog VCCIO5 Tie to 2.5 V
RSVD_IN M2 Input 1.8 V VCCIO2 Tie to GND
RSVD_IN R8 Input 1.8 V VCCIO3 Tie to GND
RSVD_IN R9 Input 1.8 V VCCIO4 Tie to GND
RSVD_IN T8 Input 1.8 V VCCIO3 Tie to GND
RSVD_IN T9 Input 1.8 V VCCIO4 Tie to GND
SENSOR_CLK B14 Output 1.8 V VCCIO7 Sensor main clock
SENSOR_DEMOD_CLK A14 Output 1.8 V VCCIO7 Demod clock for test
SENSOR_RSTZ D14 Output 1.8 V VCCIO7 Sensor reset
SLEEP B1 Input 1.8 V VCCIO1 Puts the TFC in standby mode when enabled
SYSCLK_IN E1 Input 1.8 V VCCIO1 Main system clock input
TIC_C H3 Input 2.5 V – Reserved. Needs external pull-down resistor of 10 kΩ
TIC_CEZ J3 Input 1.8 V VCCIO1 If high, TFC releases the control of configuration pins. In slave boot modes, tie to ground.
TIC_CLK H1 Input 1.8 V VCCIO1 Configuration data clock
TIC_CONFIGZ H5 Input 1.8 V VCCIO1 Used to start firmware load operation
TIC_CONF_DONE H14 Output Open Drain VCCIO6 Used to indicate end of firmware load operation
TIC_CSOZ D2 Output 1.8 V VCCIO1 In master serial boot mode, Used by TFC to load firmware from EEPROM as chip select pin.
TIC_DATA_0 H2 Input 1.8 V VCCIO1 Configuration data pin 0
TIC_DATA_1/ASDO C1 Bidir 1.8 V VCCIO1 Used as output in master serial boot mode to communicate to firmware EEPROM as data-out pin. Input in passive parallel boot mode.
TIC_DATA_2 E8 Input 1.8 V VCCIO8 Used only in Passive Parallel Boot mode. Tie to GND otherwise.
TIC_DATA_3 F8 Input 1.8 V VCCIO8 Used only in Passive Parallel Boot mode. Tie to GND otherwise.
TIC_DATA_4 B7 Input 1.8 V VCCIO8 Used only in Passive Parallel Boot mode. Tie to GND otherwise.
TIC_DATA_5 E7 Input 1.8 V VCCIO8 Used only in Passive Parallel Boot mode. Tie to GND otherwise.
TIC_DATA_6 E6 Input 1.8 V VCCIO8 Used only in Passive Parallel Boot mode. Tie to GND otherwise.
TIC_DATA_7 A5 Input 1.8 V VCCIO8 Used only in Passive Parallel Boot mode. Tie to GND otherwise.
TIC_I H4 Input 2.5 V – Reserved. Needs external pull-up resistor of 10 kΩ to 2.5 V
TIC_INIT_DONE G16 Output Open Drain VCCIO1 Used to indicate end of TFC initialization.
TIC_O J4 Output 2.5 V – Reserved. Leave unconnected.
TIC_S J5 Input 2.5 V – Reserved. Needs external pull-up resistor of 10 kΩ to 2.5 V
TIC_STATUSZ F4 Output Open Drain VCCIO1 Used to indicate status of firmware load operation
VCCA1 L5 Power – – 2.5-V supply
VCCA2 F12 Power – – 2.5-V supply
VCCA3 F5 Power – – 2.5-V supply
VCCA4 L12 Power – – 2.5-V supply
VCCD_PLL1 N4 Power – – 1.2-V supply
VCCD_PLL2 D13 Power – – 1.2-V supply
VCCD_PLL3 D4 Power – – 1.2-V supply
VCCD_PLL4 N13 Power – – 1.2-V supply
VCCINT F7 Power – – 1.2-V supply
VCCINT F11 Power – – 1.2-V supply
VCCINT G6 Power – – 1.2-V supply
VCCINT G7 Power – – 1.2-V supply
VCCINT G8 Power – – 1.2-V supply
VCCINT G9 Power – – 1.2-V supply
VCCINT G10 Power – – 1.2-V supply
VCCINT H6 Power – – 1.2-V supply
VCCINT H11 Power – – 1.2-V supply
VCCINT J6 Power – – 1.2-V supply
VCCINT K7 Power – – 1.2-V supply
VCCINT K11 Power – – 1.2-V supply
VCCIO1 E3 Power – – 1.8-V supply
VCCIO1 G3 Power – – 1.8-V supply
VCCIO2 K3 Power – – 1.8-V supply
VCCIO2 M3 Power – – 1.8-V supply
VCCIO3 P4 Power – – 1.8-V supply
VCCIO3 P7 Power – – 1.8-V supply
VCCIO3 T1 Power – – 1.8-V supply
VCCIO4 P10 Power – – 1.8-V supply
VCCIO4 P13 Power – – 1.8-V supply
VCCIO4 T16 Power – – 1.8-V supply
VCCIO5 K14 Power – – 2.5-V supply
VCCIO5 M14 Power – – 2.5-V supply
VCCIO6 E14 Power – – 3.3-V supply
VCCIO6 G14 Power – – 3.3-V supply
VCCIO7 A16 Power – – 1.8-V supply
VCCIO7 C10 Power – – 1.8-V supply
VCCIO7 C13 Power – – 1.8-V supply
VCCIO8 A1 Power – – 1.8-V supply
VCCIO8 C4 Power – – 1.8-V supply
VCCIO8 C7 Power – – 1.8-V supply
VD K1 Output 1.8 V VCCIO2 Indicates the frame boundary
VD_FR A13 Input 1.8 V VCCIO7 Sensor Frame VD
VD_IN A7 Input 1.8 V VCCIO1 External Sync input
VD_QD A10 Input 1.8 V VCCIO7 Sensor Quad VD
VD_SF A12 Input 1.8 V VCCIO7 Sensor Sub-Frame VD
VSYNC_OUT A15 Output 1.8 V VCCIO7 Sensor Sync input