SCPS178B July   2007  – April 2016 PCA9306-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Switching Characteristics: Translating Down, VIH = 3.3 V
    7. 7.7  Switching Characteristics: Translating Down, VIH = 2.5 V
    8. 7.8  Switching Characteristics: Translating Up, VIH = 2.3 V
    9. 7.9  Switching Characteristics: Translating Up, VIH = 1.5 V
    10. 7.10 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Enable (EN) Pin
      2. 9.3.2 Voltage Translation
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 General Applications of I2C
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. Bidirectional Translation
        2. Sizing Pullup Resistor
        3. PCA9306-Q1 Bandwidth
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Community Resource
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Detailed Description

9.1 Overview

The PCA9306-Q1 is a dual bidirectional I2C and SMBus voltage-level translator with an enable (EN) input that operates without the use of a direction pin. The voltage supply range for VREF1 is 1.2 V to 3.3 V and the supply range for VREF2 is 1.8 V to 5.5 V.

The PCA9306-Q1 can also be used to run two buses, one at a 400-kHz operating frequency and the other at a
100-kHz operating frequency. If the two buses are operating at different frequencies, the 100-kHz bus must be isolated by using the EN pin when the 400-kHz operation of the main bus is required. If the master is running at 400 kHz, the maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater.

In I2C applications, the bus capacitance limit of 400 pF restricts the number of devices and bus length. The capacitive load on both sides of the PCA9306-Q1 must be considered when approximating the total load of the system, ensuring the sum of both sides is under 400 pF.

Both the SDA and SCL channels of the PCA9306-Q1 have the same electrical characteristics and there is minimal deviation from one output to another in voltage or propagation delay. This characteristic is a benefit over discrete transistor voltage translation solutions, because the fabrication of the switch is symmetrical. The translator provides excellent ESD protection to lower-voltage devices and at the same time protects less ESD-resistant devices.

9.2 Functional Block Diagram

PCA9306-Q1 ld2_cps113.gif Figure 4. Logic Diagram (Positive Logic)

9.3 Feature Description

9.3.1 Enable (EN) Pin

The PCA9306-Q1 is a double-pole, single-throw switch in which the gate of the transistors is controlled by the voltage on the EN pin. In Figure 5, the PCA9306-Q1 always remains enabled when power is applied to VREF2. Figure 5, the device becomes enabled when a control signal from a processor is in a logic high state. In another variation, the EN pin can be controlled by the output of a processor, but VREF2 can be connected to a power supply through a 200-kΩ resistor. In this case, VREF2 and EN are not to be tied together and the SCL and SDA switches are in a high impedance state when EN is in a logic-low state, as shown in the Device Functional Modes section.

9.3.2 Voltage Translation

The primary feature of the PCA9306-Q1 is translating voltage from an I2C bus referenced to VREF1 up to an I2C bus referenced to VDPU, to which VREF2 is connected through a 200-kΩ pullup resistor. When translating a standard, open-drain I2C bus, this is achieved by simply connecting pullup resistors from SCL1 and SDA1 to VREF1 and connecting pullup resistors from SCL2 and SDA2 to VDPU. Find more information on sizing the pullup resistors in the Sizing Pullup Resistor section.

9.4 Device Functional Modes

Table 1 describes the two functions of the translation device.

Table 1. Function Table

H SCL1 = SCL2, SDA1 = SDA2
L Disconnect
(1) EN is controlled by the VREF2 logic levels and must be at least 1 V higher than VREF1 for best translator operation.