SCPS143G June   2009  – March 2021 PCA9548A

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Reset Timing Requirements
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 RESET Input
        1. 8.4.1.1 RESET Errata
          1. 8.4.1.1.1 System Impact
          2. 8.4.1.1.2 System Workaround
      2. 8.4.2 Power-On Reset
    5. 8.5 Programming
      1. 8.5.1 I2C Interface
    6. 8.6 Register Maps
      1. 8.6.1 Device Address
      2. 8.6.2 Control Register
      3. 8.6.3 Bus Transactions
        1. 8.6.3.1 Writes
        2. 8.6.3.2 Reads
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power-On Reset Requirements
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.6.2 Control Register

Following the successful acknowledgment of the address byte, the bus master sends a command byte that is stored in the control register in the PCA9548A (see Figure 8-5). This register can be written and read via the I2C bus. Each bit in the command byte corresponds to a SCn/SDn channel and a high (or 1) selects this channel. Multiple SCn/SDn channels may be selected at the same time. When a channel is selected, the channel becomes active after a stop condition has been placed on the I2C bus. This ensures that all SCn/SDn lines are in a high state when the channel is made active, so that no false conditions are generated at the time of connection. A stop condition always must occur immediately after the acknowledge cycle. If multiple bytes are received by the PCA9548A, it saves the last byte received.

GUID-07D372BA-9530-400C-A553-03EAAB70619C-low.gifFigure 8-5 Control Register

Table 8-2 shows the PCA9548A Command byte definition.

Table 8-2 Command Byte Definition
CONTROL REGISTER BITSCOMMAND
B7B6B5B4B3B2B1B0
XXXXXXX0Channel 0 disabled
1Channel 0 enabled
XXXXXX0XChannel 1 disabled
1Channel 1 enabled
XXXXX0XXChannel 2 disabled
1Channel 2 enabled
XXXX0XXXChannel 3 disabled
1Channel 3 enabled
XXX0XXXXChannel 4 disabled
1Channel 4 enabled
XX0XXXXXChannel 5 disabled
1Channel 5 enabled
X0XXXXXXChannel 6 disabled
1Channel 6 enabled
0XXXXXXXChannel 7 disabled
1Channel 7 enabled
00000000No channel selected, power-up/reset default state