SCPS128D July   2006  – March 2021 PCA9554


  1. Features
  2. Description
  3. Revision History
  4. Description (Continued)
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Functional Block Diagram
    2. 8.2 Device Functional Modes
      1. 8.2.1 Power-On Reset
      2. 8.2.2 I/O Port
      3. 8.2.3 Interrupt Output ( INT)
        1. Interrupt Errata
          1.        23
          2. 24
          3. 25
    3. 8.3 Programming
      1. 8.3.1 I2C Interface
      2. 8.3.2 Register Map
        1. Device Address
        2. Control Register And Command Byte
        3. Register Descriptions
        4. Bus Transactions
          1. Writes
          2. Reads
  9. Application Information Disclaimer
    1. 9.1 Application Information
      1. 9.1.1 Typical Application
        1. Design Requirements
          1. Minimizing ICC When I/Os Control Leds
  10. 10Power Supply Recommendations
    1. 10.1 Power-On Reset Requirements
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Power-On Reset Requirements

In the event of a glitch or data corruption, PCA9554 can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application.

The two types of power-on reset are shown in Figure 10-1 and Figure 10-2.

GUID-9C69E0F5-EA7B-489D-ACEC-BE801281EC5D-low.gifFigure 10-1 VCC Is Lowered Below 0.2 V Or 0 V And Then Ramped Up To VCC
GUID-E7AE7CD3-86D2-4DA9-AF3F-FE27B8571D67-low.gifFigure 10-2 VCC Is Lowered Below The Por Threshold, Then Ramped Back Up To VCC

Table 10-1 specifies the performance of the power-on reset feature for PCA9554 for both types of power-on reset.

Table 10-1 Recommended Supply Sequencing And Ramp Rates(1)
VCC_FTFall rateSee Figure 10-11100ms
VCC_RTRise rateSee Figure 10-10.01100ms
VCC_TRR_GNDTime to re-ramp (when VCC drops to GND)See Figure 10-10.001ms
VCC_TRR_POR50Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV)See Figure 10-20.001ms
VCC_GHLevel that VCCP can glitch down to, but not cause a functional disruption when VCCX_GW = 1 μsSee Figure 10-31.2V
VCC_GWGlitch width that will not cause a functional disruption when VCCX_GH = 0.5 × VCCxSee Figure 10-3μs
VPORFVoltage trip point of POR on falling VCC0.7671.144V
VPORRVoltage trip point of POR on rising VCC1.0331.428V
TA = –40°C to 85°C (unless otherwise noted)

Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and the device impedance are factors that affect power-on reset performance. Figure 10-3 and Table 10-1 provide more information on how to measure these specifications.

GUID-21907428-460E-4DF3-ABFB-4B543E3BE922-low.gifFigure 10-3 Glitch Width And Glitch Height

VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based on the VCC being lowered to or from 0. Figure 10-4 and Table 10-1 provide more details on this specification.

GUID-BB5C9265-29A6-464F-AE12-6466FC1F82EF-low.gifFigure 10-4 VPOR