SCPS068J July   2001  – March 2015 PCF8574


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
      1. 8.2.1 Simplified Block Diagram of Device
      2. 8.2.2 Simplified Schematic Diagram of Each P-Port Input/Output
    3. 8.3 Feature Description
      1. 8.3.1 I2C Interface
      2. 8.3.2 Interface Definition
      3. 8.3.3 Address Reference
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. Minimizing ICC When I/Os Control LEDs
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power-On Reset Requirements
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Application and Implementation


Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

Figure 18 shows an application in which the PCF8574 device can be used.

9.2 Typical Application

PCF8574 typ_app_cps068.gif
1. The SCL and SDA pins must be tied directly to VCC because if SCL and SDA are tied to an auxiliary power supply that could be powered on while VCC is powered off, then the supply current, ICC, will increase as a result.
B. Device address is configured as 0100000 for this example.
C. P0, P2, and P3 are configured as outputs.
D. P1, P4, and P5 are configured as inputs.
E. P6 and P7 are not used and must be configured as outputs.
Figure 18. Application Schematic

9.2.1 Design Requirements Minimizing ICC When I/Os Control LEDs

When the I/Os are used to control LEDs, normally they are connected to VCC through a resistor as shown in Figure 18. For a P-port configured as an input, ICC increases as VI becomes lower than VCC. The LED is a diode, with threshold voltage VT, and when a P-port is configured as an input the LED will be off but VI is a VT drop below VCC.

For battery-powered applications, it is essential that the voltage of P-ports controlling LEDs is greater than or equal to VCC when the P-ports are configured as input to minimize current consumption. Figure 19 shows a high-value resistor in parallel with the LED. Figure 20 shows VCC less than the LED supply voltage by at least VT. Both of these methods maintain the I/O VI at or above VCC and prevents additional supply current consumption when the P-port is configured as an input and the LED is off.

PCF8574 app_hival_r_cps126.gif Figure 19. High-Value Resistor in Parallel With LED
PCF8574 app_lowval_r_cps126.gif Figure 20. Device Supplied by a Lower Voltage

9.2.2 Detailed Design Procedure

The pull-up resistors, RP, for the SCL and SDA lines need to be selected appropriately and take into consideration the total capacitance of all slaves on the I2C bus. The minimum pull-up resistance is a function of VCC, VOL,(max), and IOL:

Equation 1. PCF8574 desc_eq1_scps068.gif

The maximum pull-up resistance is a function of the maximum rise time, tr (300 ns for fast-mode operation, fSCL = 400 kHz) and bus capacitance, Cb:

Equation 2. PCF8574 desc_eq2_cps068.gif

The maximum bus capacitance for an I2C bus must not exceed 400 pF for standard-mode or fast-mode operation. The bus capacitance can be approximated by adding the capacitance of the PCF8574 device, Ci for SCL or Cio for SDA, the capacitance of wires/connections/traces, and the capacitance of additional slaves on the bus.

9.2.3 Application Curves

PCF8574 D008_SCPS204.gif
(fSCL= 100 kHz, tr = 1 µs)
(fSCL= 400 kHz, tr= 300 ns)
Figure 21. Maximum Pull-Up resistance (Rp(max))
vs Bus Capacitance (Cb)
PCF8574 D009_SCPS199.gif
VOL = 0.2*VCC, IOL = 2 mA when VCC ≤ 2 V
VOL = 0.4 V, IOL = 3 mA when VCC > 2 V
Figure 22. Minimum Pull-Up Resistance (Rp(min))
vs Pull-Up Reference Voltage (VCC)