SCPS068J July   2001  – March 2015 PCF8574


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
      1. 8.2.1 Simplified Block Diagram of Device
      2. 8.2.2 Simplified Schematic Diagram of Each P-Port Input/Output
    3. 8.3 Feature Description
      1. 8.3.1 I2C Interface
      2. 8.3.2 Interface Definition
      3. 8.3.3 Address Reference
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. Minimizing ICC When I/Os Control LEDs
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power-On Reset Requirements
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Detailed Description

8.1 Overview

The PCF8574 device is an 8-bit I/O expander for the two-line bidirectional bus (I2C) is designed for 2.5-V to 5.5-V VCC operation. It provides general-purpose remote I/O expansion for most micro-controller families via the I2C interface (serial clock, SCL, and serial data, SDA, pins).

The PCF8574 device provides an open-drain output (INT) that can be connected to the interrupt input of a microcontroller. An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, tiv, INT is valid. Resetting and reactivating the interrupt circuit is achieved when data on the port is changed to the original setting or data is read from, or written to, the port that generated the interrupt. Resetting occurs in the read mode at the acknowledge bit after the rising edge of the SCL signal, or in the write mode at the acknowledge bit after the high-to-low transition of the SCL signal. Interrupts that occur during the acknowledge clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and, after the next rising clock edge, is transmitted as INT. Reading from, or writing to, another device does not affect the interrupt circuit. This device does not have internal configuration or status registers. Instead, read or write to the device I/Os directly after sending the device address (see Figure 16 and Figure 17).

By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate by way of the I2C bus. Therefore, PCF8574 can remain a simple slave device.

An additional strong pullup to VCC allows fast rising edges into heavily loaded outputs. This device turns on when an output is written high and is switched off by the negative edge of SCL. The I/Os should be high before being used as inputs.

8.2 Functional Block Diagram

8.2.1 Simplified Block Diagram of Device

PCF8574 LD_CPS068.gif

8.2.2 Simplified Schematic Diagram of Each P-Port Input/Output

PCF8574 simp_schem_cps068.gif

8.3 Feature Description

8.3.1 I2C Interface

I2C communication with this device is initiated by a master sending a start condition, a high-to-low transition on the SDA I/O while the SCL input is high. After the start condition, the device address byte is sent, most-significant bit (MSB) first, including the data direction bit (R/W). This device does not respond to the general call address. After receiving the valid address byte, this device responds with an acknowledge, a low on the SDA I/O during the high of the acknowledge-related clock pulse. The address inputs (A0–A2) of the slave device must not be changed between the start and the stop conditions.

The data byte follows the address acknowledge. If the R/W bit is high, the data from this device are the values read from the P port. If the R/W bit is low, the data are from the master, to be output to the P port. The data byte is followed by an acknowledge sent from this device. If other data bytes are sent from the master, following the acknowledge, they are ignored by this device. Data are output only if complete bytes are received and acknowledged. The output data will be valid at time, tpv, after the low-to-high transition of SCL and during the clock cycle for the acknowledge.

A stop condition, which is a low-to-high transition on the SDA I/O while the SCL input is high, is sent by the master.

8.3.2 Interface Definition

7 (MSB) 6 5 4 3 2 1 0 (LSB)
I2C slave address L H L L A2 A1 A0 R/W
I/O data bus P7 P6 P5 P4 P3 P2 P1 P0

8.3.3 Address Reference

A2 A1 A0
L L L 65 (decimal), 41 (hexadecimal) 64 (decimal), 40 (hexadecimal)
L L H 67 (decimal), 43 (hexadecimal) 66 (decimal), 42 (hexadecimal)
L H L 69 (decimal), 45 (hexadecimal) 68 (decimal), 44 (hexadecimal)
L H H 71 (decimal), 47 (hexadecimal) 70 (decimal), 46 (hexadecimal)
H L L 73 (decimal), 49 (hexadecimal) 72 (decimal), 48 (hexadecimal)
H L H 75 (decimal), 4B (hexadecimal) 74 (decimal), 4A (hexadecimal)
H H L 77 (decimal), 4D (hexadecimal) 76 (decimal), 4C (hexadecimal)
H H H 79 (decimal), 4F (hexadecimal) 78 (decimal), 4E (hexadecimal)

8.4 Device Functional Modes

Figure 16 and Figure 17 show the address and timing diagrams for the write and read modes, respectively.

PCF8574 write_cps068.gif Figure 16. Write Mode (Output)
PCF8574 read_cps068.gif
A. A low-to-high transition of SDA while SCL is high is defined as the stop condition (P). The transfer of data can be stopped at any moment bya stop condition. When this occurs, data present at the latest ACK phase is valid (output mode). Input data is lost.
Figure 17. Read Mode (Input)