SCPS068J July 2001 – March 2015 PCF8574
In the event of a glitch or data corruption, the PCF8574 device can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application.
Table 1 specifies the performance of the power-on reset feature for PCF8574 for both types of power-on reset.
|VCC_FT||Fall rate||See Figure 23||1||100||ms|
|VCC_RT||Rise rate||See Figure 23||0.01||100||ms|
|VCC_TRR_GND||Time to re-ramp (when VCC drops to GND)||See Figure 23||0.001||ms|
|VCC_TRR_POR50||Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV)||See Figure 24||0.001||ms|
|VCC_GH||Level that VCCP can glitch down to, but not cause a functional disruption when VCCX_GW = 1 μs||See Figure 25||1.2||V|
|VCC_GW||Glitch width that will not cause a functional disruption when VCCX_GH = 0.5 × VCCx||See Figure 25||μs|
|VPORF||Voltage trip point of POR on falling VCC||0.767||1.144||V|
|VPORR||Voltage trip point of POR on fising VCC||1.033||1.428||V|
Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 25 and Table 1 provide more information on how to measure these specifications.
VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based on the VCC being lowered to or from 0. Figure 26 and Table 1 provide more details on this specification.