SBASAH0A April 2022 – September 2022 PCM3120-Q1
PRODUCTION DATA
Table 8-107 lists the memory-mapped registers for the Page 1 registers. All register offset addresses not listed in Table 8-107 should be considered as reserved locations and the register contents should not be modified.
| Address | Acronym | Register Name | Reset Value | Section |
|---|---|---|---|---|
| 0x0 | PAGE_CFG | Device page register | 0x00 | #PAGE_1_PAGE_1_PAGE_1_PAGE_CFG |
| 0x1E | VAD_CFG1 | Voice activity detection configuration register 1 | 0x20 | #PAGE_1_PAGE_1_PAGE_1_VAD_CFG1 |
| 0x1F | VAD_CFG2 | Voice activity detection configuration register 2 | 0x08 | #PAGE_1_PAGE_1_PAGE_1_VAD_CFG2 |
PAGE_CFG is shown in Table 8-108.
Return to the Summary Table.
The device memory map is divided into pages. This register sets the page.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | PAGE[7:0] | R/W | 00000000b | These bits set the device page.
0d = Page 0 1d = Page 1 2d to 254d = Page 2 to page 254 respectively 255d = Page 255 |
VAD_CFG1 is shown in Table 8-109.
Return to the Summary Table.
This register is configuration register 1 for voice activity detection.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | VAD_MODE[1:0] | R/W | 00b | Auto ADC power up / power down configuration selection.
0d = User initiated ADC power-up and ADC power-down 1d = VAD interrupt based ADC power up and ADC power down 2d = VAD interrupt based ADC power up but user initiated ADC power down 3d = User initiated ADC power-up but VAD interrupt based ADC power down |
| 5-4 | VAD_CH_SEL[1:0] | R/W | 10b | VAD channel select.
0d = Channel 1 is monitored for VAD activity 1d = Channel 2 is monitored for VAD activity 2d = Channel 3 is monitored for VAD activity 3d = Channel 4 is monitored for VAD activity |
| 3-2 | VAD_CLK_CFG[1:0] | R/W | 00b | Clock select for VAD
0d = VAD processing using internal oscillator clock 1d = VAD processing using external clock on BCLK input 2d = VAD processing using external clock on MCLK input 3d = Custom clock configuration based on MST_CFG, CLK_SRC and CLKGEN_CFG registers in page 0 |
| 1-0 | VAD_EXT_CLK_CFG[1:0] | R/W | 00b | Clock configuration using external clock for VAD.
0d = External clock is 3.072 MHz 1d = External clock is 6.144 MHz 2d = External clock is 12.288 MHz 3d = External clock is 18.432 MHz |
VAD_CFG2 is shown in Table 8-110.
Return to the Summary Table.
This register is configuration register 2 for voice activity detection.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
| 6 | SDOUT_INT_CFG | R/W | 0b | SDOUT interrupt configuration.
0d = SDOUT pin is not enabled for interrupt function 1d = SDOUT pin is enabled to support interrupt output when channel data in not being recorded |
| 5 | RESERVED | R | 0b | Reserved bit; Write only reset value |
| 4 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
| 3 | VAD_PD_DET_EN | R/W | 1b | Enable ASI output data during VAD activity.
0d = VAD processing is not enabled during ADC recording 1d = VAD processing is enabled during ADC recording and VAD interrupts are generated as configured |
| 2-0 | RESERVED | R | 000b | Reserved bits; Write only reset values |