SBASAH0A April   2022  – September 2022 PCM3120-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4.     Thermal Information
    5. 7.4  Electrical Characteristics
    6. 7.5  Timing Requirements: I2C Interface
    7. 7.6  Switching Characteristics: I2C Interface
    8. 7.7  Timing Requirements: TDM, I2S or LJ Interface
    9. 7.8  Switching Characteristics: TDM, I2S or LJ Interface
    10.     Timing Requirements: PDM Digital Microphone Interface
    11. 7.9  Switching Characteristics: PDM Digial Microphone Interface
    12. 7.10 Timing Diagrams
    13. 7.11 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Serial Interfaces
        1. 8.3.1.1 Control Serial Interfaces
        2. 8.3.1.2 Audio Serial Interfaces
          1. 8.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 8.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 8.3.1.2.3 Left-Justified (LJ) Interface
        3. 8.3.1.3 Using Multiple Devices With Shared Buses
      2. 8.3.2  Phase-Locked Loop (PLL) and Clock Generation
      3. 8.3.3  Input Channel Configurations
      4. 8.3.4  Reference Voltage
      5. 8.3.5  Programmable Microphone Bias
      6. 8.3.6  Signal-Chain Processing
        1. 8.3.6.1 Programmable Channel Gain and Digital Volume Control
        2. 8.3.6.2 Programmable Channel Gain Calibration
        3. 8.3.6.3 Programmable Channel Phase Calibration
        4. 8.3.6.4 Programmable Digital High-Pass Filter
        5. 8.3.6.5 Programmable Digital Biquad Filters
        6. 8.3.6.6 Programmable Channel Summer and Digital Mixer
        7. 8.3.6.7 Configurable Digital Decimation Filters
          1. 8.3.6.7.1 Linear Phase Filters
            1. 8.3.6.7.1.1 Sampling Rate: 7.35 kHz to 8 kHz
            2. 8.3.6.7.1.2 Sampling Rate: 14.7 kHz to 16 kHz
            3. 8.3.6.7.1.3 Sampling Rate: 22.05 kHz to 24 kHz
            4. 8.3.6.7.1.4 Sampling Rate: 29.4 kHz to 32 kHz
            5. 8.3.6.7.1.5 Sampling Rate: 44.1 kHz to 48 kHz
            6. 8.3.6.7.1.6 Sampling Rate: 88.2 kHz to 96 kHz
            7. 8.3.6.7.1.7 Sampling Rate: 176.4 kHz to 192 kHz
            8. 8.3.6.7.1.8 Sampling Rate: 352.8 kHz to 384 kHz
            9. 8.3.6.7.1.9 Sampling Rate: 705.6 kHz to 768 kHz
          2. 8.3.6.7.2 Low-Latency Filters
            1. 8.3.6.7.2.1 Sampling Rate: 14.7 kHz to 16 kHz
            2. 8.3.6.7.2.2 Sampling Rate: 22.05 kHz to 24 kHz
            3. 8.3.6.7.2.3 Sampling Rate: 29.4 kHz to 32 kHz
            4. 8.3.6.7.2.4 Sampling Rate: 44.1 kHz to 48 kHz
            5. 8.3.6.7.2.5 Sampling Rate: 88.2 kHz to 96 kHz
            6. 8.3.6.7.2.6 Sampling Rate: 176.4 kHz to 192 kHz
          3. 8.3.6.7.3 Ultra-Low Latency Filters
            1. 8.3.6.7.3.1 Sampling Rate: 14.7 kHz to 16 kHz
            2. 8.3.6.7.3.2 Sampling Rate: 22.05 kHz to 24 kHz
            3. 8.3.6.7.3.3 Sampling Rate: 29.4 kHz to 32 kHz
            4. 8.3.6.7.3.4 Sampling Rate: 44.1 kHz to 48 kHz
            5. 8.3.6.7.3.5 Sampling Rate: 88.2 kHz to 96 kHz
            6. 8.3.6.7.3.6 Sampling Rate: 176.4 kHz to 192 kHz
            7. 8.3.6.7.3.7 Sampling Rate: 352.8 kHz to 384 kHz
      7. 8.3.7  Automatic Gain Controller (AGC)
      8. 8.3.8  Voice Activity Detection (VAD)
      9. 8.3.9  Digital PDM Microphone Record Channel
      10. 8.3.10 Interrupts, Status, and Digital I/O Pin Multiplexing
    4. 8.4 Device Functional Modes
      1. 8.4.1 Sleep Mode or Software Shutdown
      2. 8.4.2 Active Mode
      3. 8.4.3 Software Reset
    5. 8.5 Programming
      1. 8.5.1 Control Serial Interfaces
        1. 8.5.1.1 I2C Control Interface
          1. 8.5.1.1.1 General I2C Operation
            1. 8.5.1.1.1.1 I2C Single-Byte and Multiple-Byte Transfers
              1. 8.5.1.1.1.1.1 I2C Single-Byte Write
              2. 8.5.1.1.1.1.2 I2C Multiple-Byte Write
              3. 8.5.1.1.1.1.3 I2C Single-Byte Read
              4. 8.5.1.1.1.1.4 I2C Multiple-Byte Read
    6. 8.6 Register Maps
      1. 8.6.1 Device Configuration Registers
        1. 8.6.1.1 PCM3120-Q1 Access Codes
      2. 8.6.2 Page 0 Registers
      3. 8.6.3 Page 1 Registers
      4. 8.6.4 Programmable Coefficient Registers
        1. 8.6.4.1 Programmable Coefficient Registers: Page 2
        2. 8.6.4.2 Programmable Coefficient Registers: Page 3
        3. 8.6.4.3 Programmable Coefficient Registers: Page 4
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Two-Channel Analog Microphone Recording
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Example Device Register Configuration Script for EVM Setup
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Four-Channel Digital PDM Microphone Recording
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Example Device Register Configuration Script for EVM Setup
    3. 9.3 What to Do and What Not to Do
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.6.2 Page 0 Registers

Table 8-51 lists the memory-mapped registers for the Page 0 registers. All register offset addresses not listed in Table 8-51 should be considered as reserved locations and the register contents should not be modified.

Table 8-51 PAGE 0 Registers
AddressAcronymRegister NameReset ValueSection
0x0PAGE_CFGDevice page register0x00#PAGE_0_PAGE_0_PAGE_0_PAGE_CFG
0x1SW_RESETSoftware reset register0x00#PAGE_0_PAGE_0_PAGE_0_SW_RESET
0x2SLEEP_CFGSleep mode register0x00#PAGE_0_PAGE_0_PAGE_0_SLEEP_CFG
0x5SHDN_CFGShutdown configuration register0x05#PAGE_0_PAGE_0_PAGE_0_SHDN_CFG
0x7ASI_CFG0ASI configuration register 00x30#PAGE_0_PAGE_0_PAGE_0_ASI_CFG0
0x8ASI_CFG1ASI configuration register 10x00#PAGE_0_PAGE_0_PAGE_0_ASI_CFG1
0x9ASI_CFG2ASI configuration register 20x00#PAGE_0_PAGE_0_PAGE_0_ASI_CFG2
0xAASI_MIX_CFGASI input mixing configuration register0x00#PAGE_0_PAGE_0_PAGE_0_ASI_MIX_CFG
0xBASI_CH1Channel 1 ASI slot configuration register0x00#PAGE_0_PAGE_0_PAGE_0_ASI_CH1
0xCASI_CH2Channel 2 ASI slot configuration register0x01#PAGE_0_PAGE_0_PAGE_0_ASI_CH2
0xDASI_CH3Channel 3 ASI slot configuration register0x02#PAGE_0_PAGE_0_PAGE_0_ASI_CH3
0xEASI_CH4Channel 4 ASI slot configuration register0x03#PAGE_0_PAGE_0_PAGE_0_ASI_CH4
0x13MST_CFG0ASI master mode configuration register 00x02#PAGE_0_PAGE_0_PAGE_0_MST_CFG0
0x14MST_CFG1ASI master mode configuration register 10x48#PAGE_0_PAGE_0_PAGE_0_MST_CFG1
0x15ASI_STSASI bus clock monitor status register0xFF#PAGE_0_PAGE_0_PAGE_0_ASI_STS
0x16CLK_SRCClock source configuration register 00x10#PAGE_0_PAGE_0_PAGE_0_CLK_SRC
0x1FPDMCLK_CFGPDM clock generation configuration register0x40#PAGE_0_PAGE_0_PAGE_0_PDMCLK_CFG
0x20PDMIN_CFGPDM DINx sampling edge register0x00#PAGE_0_PAGE_0_PAGE_0_PDMIN_CFG
0x21GPIO_CFG0GPIO configuration register 00x22#PAGE_0_PAGE_0_PAGE_0_GPIO_CFG0
0x22GPO_CFG0GPO configuration register 00x00#PAGE_0_PAGE_0_PAGE_0_GPO_CFG0
0x29GPO_VALGPIO, GPO output value register0x00#PAGE_0_PAGE_0_PAGE_0_GPO_VAL
0x2AGPIO_MONGPIO monitor value register0x00#PAGE_0_PAGE_0_PAGE_0_GPIO_MON
0x2BGPI_CFG0GPI configuration register 00x00#PAGE_0_PAGE_0_PAGE_0_GPI_CFG0
0x2FGPI_MONGPI monitor value register0x00#PAGE_0_PAGE_0_PAGE_0_GPI_MON
0x32INT_CFGInterrupt configuration register0x00#PAGE_0_PAGE_0_PAGE_0_INT_CFG
0x33INT_MASK0Interrupt mask register 00xFF#PAGE_0_PAGE_0_PAGE_0_INT_MASK0
0x36INT_LTCH0Latched interrupt readback register 00x00#PAGE_0_PAGE_0_PAGE_0_INT_LTCH0
0x3ACM_TOL_CFGADC common mode configuration register0x00#PAGE_0_PAGE_0_PAGE_0_CM_TOL_CFG
0x3BBIAS_CFGBias and ADC configuration register0x00#PAGE_0_PAGE_0_PAGE_0_BIAS_CFG
0x3CCH1_CFG0Channel 1 configuration register 00x00#PAGE_0_PAGE_0_PAGE_0_CH1_CFG0
0x3DCH1_CFG1Channel 1 configuration register 10x00#PAGE_0_PAGE_0_PAGE_0_CH1_CFG1
0x3ECH1_CFG2Channel 1 configuration register 20xC9#PAGE_0_PAGE_0_PAGE_0_CH1_CFG2
0x3FCH1_CFG3Channel 1 configuration register 30x80#PAGE_0_PAGE_0_PAGE_0_CH1_CFG3
0x40CH1_CFG4Channel 1 configuration register 40x00#PAGE_0_PAGE_0_PAGE_0_CH1_CFG4
0x41CH2_CFG0Channel 2 configuration register 00x00#PAGE_0_PAGE_0_PAGE_0_CH2_CFG0
0x42CH2_CFG1Channel 2 configuration register 10x00#PAGE_0_PAGE_0_PAGE_0_CH2_CFG1
0x43CH2_CFG2Channel 2 configuration register 20xC9#PAGE_0_PAGE_0_PAGE_0_CH2_CFG2
0x44CH2_CFG3Channel 2 configuration register 30x80#PAGE_0_PAGE_0_PAGE_0_CH2_CFG3
0x45CH2_CFG4Channel 2 configuration register 40x00#PAGE_0_PAGE_0_PAGE_0_CH2_CFG4
0x48CH3_CFG2Channel 3 configuration register 20xC9#PAGE_0_PAGE_0_PAGE_0_CH3_CFG2
0x49CH3_CFG3Channel 3 configuration register 30x80#PAGE_0_PAGE_0_PAGE_0_CH3_CFG3
0x4ACH3_CFG4Channel 3 configuration register 40x00#PAGE_0_PAGE_0_PAGE_0_CH3_CFG4
0x4DCH4_CFG2Channel 4 configuration register 20xC9#PAGE_0_PAGE_0_PAGE_0_CH4_CFG2
0x4ECH4_CFG3Channel 4 configuration register 30x80#PAGE_0_PAGE_0_PAGE_0_CH4_CFG3
0x4FCH4_CFG4Channel 4 configuration register 40x00#PAGE_0_PAGE_0_PAGE_0_CH4_CFG4
0x6BDSP_CFG0DSP configuration register 00x01#PAGE_0_PAGE_0_PAGE_0_DSP_CFG0
0x6CDSP_CFG1DSP configuration register 10x40#PAGE_0_PAGE_0_PAGE_0_DSP_CFG1
0x70AGC_CFG0AGC configuration register 00xE7#PAGE_0_PAGE_0_PAGE_0_AGC_CFG0
0x71GAIN_CFGGain change Configuration0x00#PAGE_0_PAGE_0_PAGE_0_GAIN_CFG
0x73IN_CH_ENInput channel enable configuration register0xC0#PAGE_0_PAGE_0_PAGE_0_IN_CH_EN
0x74ASI_OUT_CH_ENASI output channel enable configuration register0x00#PAGE_0_PAGE_0_PAGE_0_ASI_OUT_CH_EN
0x75PWR_CFGPower up configuration register0x00#PAGE_0_PAGE_0_PAGE_0_PWR_CFG
0x76DEV_STS0Device status value register 00x00#PAGE_0_PAGE_0_PAGE_0_DEV_STS0
0x77DEV_STS1Device status value register 10x80#PAGE_0_PAGE_0_PAGE_0_DEV_STS1
0x7EI2C_CKSUMI2C checksum register0x00#PAGE_0_PAGE_0_PAGE_0_I2C_CKSUM

8.6.2.1 PAGE_CFG Register (Address = 0x0) [Reset = 0x00]

PAGE_CFG is shown in Table 8-52.

Return to the Summary Table.

The device memory map is divided into pages. This register sets the page.

Table 8-52 PAGE_CFG Register Field Descriptions
BitFieldTypeResetDescription
7-0PAGE[7:0]R/W00000000bThese bits set the device page.
0d = Page 0
1d = Page 1
2d to 254d = Page 2 to page 254 respectively
255d = Page 255

8.6.2.2 SW_RESET Register (Address = 0x1) [Reset = 0x00]

SW_RESET is shown in Table 8-53.

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This register is the software reset register. Asserting a software reset places all register values in their default power-on-reset (POR) state.

Table 8-53 SW_RESET Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR0000000bReserved bits; Write only reset value
0SW_RESETR/W0bSoftware reset. This bit is self clearing.
0d = Do not reset
1d = Reset all registers to their reset values

8.6.2.3 SLEEP_CFG Register (Address = 0x2) [Reset = 0x00]

SLEEP_CFG is shown in Table 8-54.

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This register configures the regulator, VREF quick charge, I2C broadcast and sleep mode.

Table 8-54 SLEEP_CFG Register Field Descriptions
BitFieldTypeResetDescription
7AREG_SELECTR/W0bThe analog supply selection from either the internal regulator supply or the external AREG supply.
0d = External 1.8-V AREG supply (use this setting when AVDD is 1.8 V and short AREG with AVDD)
1d = Internally generated 1.8-V AREG supply using an on-chip regulator (use this setting when AVDD is 3.3 V)
6-5RESERVEDR/W00bReserved bits; Write only reset values
4-3VREF_QCHG[1:0]R/W00bThe duration of the quick-charge for the VREF external capacitor is set using an internal series impedance of 200 Ω.
0d = VREF quick-charge duration of 3.5 ms (typical)
1d = VREF quick-charge duration of 10 ms (typical)
2d = VREF quick-charge duration of 50 ms (typical)
3d = VREF quick-charge duration of 100 ms (typical)
2I2C_BRDCAST_ENR/W0b I2C broadcast addressing setting.
0d = I2C broadcast mode disabled
1d = I2C broadcast mode enabled; the I2C target address is fixed at 1001 100
1RESERVEDR0bReserved bit; Write only reset value
0SLEEP_ENZR/W0bSleep mode setting.
0d = Device is in sleep mode
1d = Device is not in sleep mode

8.6.2.4 SHDN_CFG Register (Address = 0x5) [Reset = 0x05]

SHDN_CFG is shown in Table 8-55.

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This register configures the device shutdown

Table 8-55 SHDN_CFG Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR00bReserved bits; Write only reset value
5-4INCAP_QCHG[1:0]R/W00bThe duration of the quick-charge for the external AC-coupling capacitor is set using an internal series impedance of 800 Ω.
0d = INxP, INxM quick-charge duration of 2.5 ms (typical)
1d = INxP, INxM quick-charge duration of 12.5 ms (typical)
2d = INxP, INxM quick-charge duration of 25 ms (typical)
3d = INxP, INxM quick-charge duration of 50 ms (typical)
3-2RESERVEDR/W01bReserved bits; Write only reset values
1-0RESERVEDR/W01bReserved bits; Write only reset values

8.6.2.5 ASI_CFG0 Register (Address = 0x7) [Reset = 0x30]

ASI_CFG0 is shown in Table 8-56.

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This register is the ASI configuration register 0.

Table 8-56 ASI_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7-6ASI_FORMAT[1:0]R/W00bASI protocol format.
0d = TDM mode
1d = I2S mode
2d = LJ (left-justified) mode
3d = Reserved; Don't use
5-4ASI_WLEN[1:0]R/W11bASI word or slot length.
0d = 16 bits (Recommended this setting to be used with 10-kΩ or 20-kΩ input impedance configuration)
1d = 20 bits
2d = 24 bits
3d = 32 bits
3FSYNC_POLR/W0bASI FSYNC polarity.
0d = Default polarity as per standard protocol
1d = Inverted polarity with respect to standard protocol
2BCLK_POLR/W0bASI BCLK polarity.
0d = Default polarity as per standard protocol
1d = Inverted polarity with respect to standard protocol
1TX_EDGER/W0bASI data output (on the primary and secondary data pin) transmit edge.
0d = Default edge as per the protocol configuration setting in bit 2 (BCLK_POL)
1d = Inverted following edge (half cycle delay) with respect to the default edge setting
0TX_FILLR/W0bASI data output (on the primary and secondary data pin) for any unused cycles
0d = Always transmit 0 for unused cycles
1d = Always use Hi-Z for unused cycles

8.6.2.6 ASI_CFG1 Register (Address = 0x8) [Reset = 0x00]

ASI_CFG1 is shown in Table 8-57.

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This register is the ASI configuration register 1.

Table 8-57 ASI_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7TX_LSBR/W0bASI data output (on the primary and secondary data pin) for LSB transmissions.
0d = Transmit the LSB for a full cycle
1d = Transmit the LSB for the first half cycle and Hi-Z for the second half cycle
6-5TX_KEEPER[1:0]R/W00bASI data output (on the primary and secondary data pin) bus keeper.
0d = Bus keeper is always disabled
1d = Bus keeper is always enabled
2d = Bus keeper is enabled during LSB transmissions only for one cycle
3d = Bus keeper is enabled during LSB transmissions only for one and half cycles
4-0TX_OFFSET[4:0]R/W00000bASI data MSB slot 0 offset (on the primary and secondary data pin).
0d = ASI data MSB location has no offset and is as per standard protocol
1d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is the left and right slot 0) offset of one BCLK cycle with respect to standard protocol
2d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is the left and right slot 0) offset of two BCLK cycles with respect to standard protocol
3d to 30d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is the left and right slot 0) offset assigned as per configuration
31d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is the left and right slot 0) offset of 31 BCLK cycles with respect to standard protocol

8.6.2.7 ASI_CFG2 Register (Address = 0x9) [Reset = 0x00]

ASI_CFG2 is shown in Table 8-58.

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This register is the ASI configuration register 2.

Table 8-58 ASI_CFG2 Register Field Descriptions
BitFieldTypeResetDescription
7ASI_DAISYR/W0bASI daisy chain connection.
0d = All devices are connected in the common ASI bus
1d = All devices are daisy-chained for the ASI bus. This is supported only if ASI input mixing is disabled, refer register 10 for details on ASI input mixing feature.
6RESERVEDR0bReserved bit; Write only reset value
5ASI_ERRR/W0bASI bus error detection.
0d = Enable bus error detection
1d = Disable bus error detection
4ASI_ERR_RCOVR/W0bASI bus error auto resume.
0d = Enable auto resume after bus error recovery
1d = Disable auto resume after bus error recovery and remain powered down until the host configures the device
3RESERVEDR/W0bReserved bit; Write only reset value
2-0RESERVEDR000bReserved bits; Write only reset value

8.6.2.8 ASI_MIX_CFG Register (Address = 0xA) [Reset = 0x00]

ASI_MIX_CFG is shown in Table 8-59.

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This register is the ASI input mixing configuration register.

Table 8-59 ASI_MIX_CFG Register Field Descriptions
BitFieldTypeResetDescription
7-6ASI_MIX_SEL[1:0]R/W00bASI input (from GPIx or GPIO) mixing selection with channel data.
0d = No mixing
1d = Channel 1 and channel 2 output data mixed with ASI input data on channel 1 (slot 0)
2d = Channel 1 and channel 2 output data mixed with ASI input data on channel 2 (slot 1)
3d = Mixed both channel data with ASI input data independently. Mixed asi_in_ch_1 with channel 1 output data and similarly mix asi_in_ch_2 with channel 2 output data
5-4ASI_GAIN_SEL[1:0]R/W00bASI input data gain selection before mixing to channel data.
0d = No gain
1d = Gain asi input data by -6dB
2d = Gain asi input data by -12dB
3d = Gain asi input data by -18dB
3ASI_IN_INVERSER/W0bInvert ASI input data before mixing to channel data.
0d = No inversion done for ASI input data
1d = ASI input data inverted before mixing with channel data
2RESERVEDR0bReserved bit; Write only reset value
1RESERVEDR0bReserved bit; Write only reset value
0RESERVEDR0bReserved bit; Write only reset value

8.6.2.9 ASI_CH1 Register (Address = 0xB) [Reset = 0x00]

ASI_CH1 is shown in Table 8-60.

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This register is the ASI slot configuration register for channel 1.

Table 8-60 ASI_CH1 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR00bReserved bits; Write only reset value
5-0CH1_SLOT[5:0]R/W000000bChannel 1 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is left slot 31
32d = TDM is slot 32 or I2S, LJ is right slot 0
33d = TDM is slot 33 or I2S, LJ is right slot 1
34d to 62d = Slot assigned as per configuration
63d = TDM is slot 63 or I2S, LJ is right slot 31

8.6.2.10 ASI_CH2 Register (Address = 0xC) [Reset = 0x01]

ASI_CH2 is shown in Table 8-61.

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This register is the ASI slot configuration register for channel 2.

Table 8-61 ASI_CH2 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR00bReserved bits; Write only reset value
5-0CH2_SLOT[5:0]R/W000001bChannel 2 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is left slot 31
32d = TDM is slot 32 or I2S, LJ is right slot 0
33d = TDM is slot 33 or I2S, LJ is right slot 1
34d to 62d = Slot assigned as per configuration
63d = TDM is slot 63 or I2S, LJ is right slot 31

8.6.2.11 ASI_CH3 Register (Address = 0xD) [Reset = 0x02]

ASI_CH3 is shown in Table 8-62.

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This register is the ASI slot configuration register for channel 3.

Table 8-62 ASI_CH3 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR00bReserved bits; Write only reset value
5-0CH3_SLOT[5:0]R/W000010bChannel 3 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is left slot 31
32d = TDM is slot 32 or I2S, LJ is right slot 0
33d = TDM is slot 33 or I2S, LJ is right slot 1
34d to 62d = Slot assigned as per configuration
63d = TDM is slot 63 or I2S, LJ is right slot 31

8.6.2.12 ASI_CH4 Register (Address = 0xE) [Reset = 0x03]

ASI_CH4 is shown in Table 8-63.

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This register is the ASI slot configuration register for channel 4.

Table 8-63 ASI_CH4 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR00bReserved bits; Write only reset value
5-0CH4_SLOT[5:0]R/W000011bChannel 4 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is left slot 31
32d = TDM is slot 32 or I2S, LJ is right slot 0
33d = TDM is slot 33 or I2S, LJ is right slot 1
34d to 62d = Slot assigned as per configuration
63d = TDM is slot 63 or I2S, LJ is right slot 31

8.6.2.13 MST_CFG0 Register (Address = 0x13) [Reset = 0x02]

MST_CFG0 is shown in Table 8-64.

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This register is the ASI master mode configuration register 0.

Table 8-64 MST_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7MST_SLV_CFGR/W0bASI master or slave configuration register setting.
0d = Device is in slave mode (both BCLK and FSYNC are inputs to the device)
1d = Device is in master mode (both BCLK and FSYNC are generated from the device)
6AUTO_CLK_CFGR/W0bAutomatic clock configuration setting.
0d = Auto clock configuration is enabled (all internal clock divider and PLL configurations are auto derived)
1d = Auto clock configuration is disabled (custom mode and device GUI must be used for the device configuration settings)
5AUTO_MODE_PLL_DISR/W0bAutomatic mode PLL setting.
0d = PLL is enabled in auto clock configuration
1d = PLL is disabled in auto clock configuration
4BCLK_FSYNC_GATER/W0bBCLK and FSYNC clock gate (valid when the device is in master mode).
0d = Do not gate BCLK and FSYNC
1d = Force gate BCLK and FSYNC when being transmitted from the device in master mode
3FS_MODER/W0bSample rate setting (valid when the device is in master mode).
0d = fS is a multiple (or submultiple) of 48 kHz
1d = fS is a multiple (or submultiple) of 44.1 kHz
2-0MCLK_FREQ_SEL[2:0]R/W010bThese bits select the MCLK (GPIO or GPIx) frequency for the PLL source clock input (valid when the device is in master mode and MCLK_FREQ_SEL_MODE = 0).
0d = 12 MHz
1d = 12.288 MHz
2d = 13 MHz
3d = 16 MHz
4d = 19.2 MHz
5d = 19.68 MHz
6d = 24 MHz
7d = 24.576 MHz

8.6.2.14 MST_CFG1 Register (Address = 0x14) [Reset = 0x48]

MST_CFG1 is shown in Table 8-65.

Return to the Summary Table.

This register is the ASI master mode configuration register 1.

Table 8-65 MST_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7-4FS_RATE[3:0]R/W0100bProgrammed sample rate of the ASI bus (not used when the device is configured in slave mode auto clock configuration).
0d = 7.35 kHz or 8 kHz
1d = 14.7 kHz or 16 kHz
2d = 22.05 kHz or 24 kHz
3d = 29.4 kHz or 32 kHz
4d = 44.1 kHz or 48 kHz
5d = 88.2 kHz or 96 kHz
6d = 176.4 kHz or 192 kHz
7d = 352.8 kHz or 384 kHz
8d = 705.6 kHz or 768 kHz
9d to 15d = Reserved; Don't use
3-0FS_BCLK_RATIO[3:0]R/W1000bProgrammed BCLK to FSYNC frequency ratio of the ASI bus (not used when the device is configured in slave mode auto clock configuration).
0d = Ratio of 16
1d = Ratio of 24
2d = Ratio of 32
3d = Ratio of 48
4d = Ratio of 64
5d = Ratio of 96
6d = Ratio of 128
7d = Ratio of 192
8d = Ratio of 256
9d = Ratio of 384
10d = Ratio of 512
11d = Ratio of 1024
12d = Ratio of 2048
13d to 15d = Reserved; Don't use

8.6.2.15 ASI_STS Register (Address = 0x15) [Reset = 0xFF]

ASI_STS is shown in Table 8-66.

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This register s the ASI bus clock monitor status register

Table 8-66 ASI_STS Register Field Descriptions
BitFieldTypeResetDescription
7-4FS_RATE_STS[3:0]R1111bDetected sample rate of the ASI bus.
0d = 7.35 kHz or 8 kHz
1d = 14.7 kHz or 16 kHz
2d = 22.05 kHz or 24 kHz
3d = 29.4 kHz or 32 kHz
4d = 44.1 kHz or 48 kHz
5d = 88.2 kHz or 96 kHz
6d = 176.4 kHz or 192 kHz
7d = 352.8 kHz or 384 kHz
8d = 705.6 kHz or 768 kHz
9d to 14d = Reserved status
15d = Invalid sample rate
3-0FS_RATIO_STS[3:0]R1111bDetected BCLK to FSYNC frequency ratio of the ASI bus.
0d = Ratio of 16
1d = Ratio of 24
2d = Ratio of 32
3d = Ratio of 48
4d = Ratio of 64
5d = Ratio of 96
6d = Ratio of 128
7d = Ratio of 192
8d = Ratio of 256
9d = Ratio of 384
10d = Ratio of 512
11d = Ratio of 1024
12d = Ratio of 2048
13d to 14d = Reserved status
15d = Invalid ratio

8.6.2.16 CLK_SRC Register (Address = 0x16) [Reset = 0x10]

CLK_SRC is shown in Table 8-67.

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This register is the clock source configuration register.

Table 8-67 CLK_SRC Register Field Descriptions
BitFieldTypeResetDescription
7DIS_PLL_SLV_CLK_SRCR/W0bAudio root clock source setting when the device is configured with the PLL disabled in the auto clock configuration for slave mode (AUTO_MODE_PLL_DIS = 1).
0d = BCLK is used as the audio root clock source
1d = MCLK (GPIO or GPIx) is used as the audio root clock source (the MCLK to FSYNC ratio is as per MCLK_RATIO_SEL setting)
6MCLK_FREQ_SEL_MODER/W0bMaster mode MCLK (GPIO or GPIx) frequency selection mode (valid when the device is in auto clock configuration).
0d = MCLK frequency is based on the MCLK_FREQ_SEL (P0_R19) configuration
1d = MCLK frequency is specified as a multiple of FSYNC in the MCLK_RATIO_SEL (P0_R22) configuration
5-3MCLK_RATIO_SEL[2:0]R/W010bThese bits select the MCLK (GPIO or GPIx) to FSYNC ratio for master mode or when MCLK is used as the audio root clock source in slave mode.
0d = Ratio of 64
1d = Ratio of 256
2d = Ratio of 384
3d = Ratio of 512
4d = Ratio of 768
5d = Ratio of 1024
6d = Ratio of 1536
7d = Ratio of 2304
2RESERVEDR/W0bReserved bit; Write only reset value
1INV_BCLK_FOR_FSYNCR/W0bInvert BCLK polarity only for FSYNC generation in master mode configuration.
0d = Do not invert BCLK polarity for FSYNC generation
1d = Invert BCLK polarity for FSYNC generation
0RESERVEDR/W0bReserved bit; Write only reset value

8.6.2.17 PDMCLK_CFG Register (Address = 0x1F) [Reset = 0x40]

PDMCLK_CFG is shown in Table 8-68.

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This register is the PDM clock generation configuration register.

Table 8-68 PDMCLK_CFG Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0bReserved bit; Write only reset value
6-2RESERVEDR/W10000bReserved bits; Write only reset values
1-0PDMCLK_DIV[1:0]R/W00bPDMCLK divider value.
0d = PDMCLK is 2.8224 MHz or 3.072 MHz
1d = PDMCLK is 1.4112 MHz or 1.536 MHz
2d = PDMCLK is 705.6 kHz or 768 kHz
3d = PDMCLK is 5.6448 MHz or 6.144 MHz (applicable only for PDM channel 1 and 2)

8.6.2.18 PDMIN_CFG Register (Address = 0x20) [Reset = 0x00]

PDMIN_CFG is shown in Table 8-69.

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This register is the PDM DINx sampling edge configuration register.

Table 8-69 PDMIN_CFG Register Field Descriptions
BitFieldTypeResetDescription
7PDMDIN1_EDGER/W0bPDMCLK latching edge used for channel 1 and channel 2 data.
0d = Channel 1 data are latched on the negative edge, channel 2 data are latched on the positive edge
1d = Channel 1 data are latched on the positive edge, channel 2 data are latched on the negative edge
6RESERVEDR/W0bReserved bit; Write only reset value
5-0RESERVEDR000000bReserved bits; Write only reset value

8.6.2.19 GPIO_CFG0 Register (Address = 0x21) [Reset = 0x22]

GPIO_CFG0 is shown in Table 8-70.

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This register is the GPIO configuration register 0.

Table 8-70 GPIO_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7-4GPIO1_CFG[3:0]R/W0010bGPIO1 configuration.
0d = GPIO1 is disabled
1d = GPIO1 is configured as a general-purpose output (GPO)
2d = GPIO1 is configured as a device interrupt output (IRQ)
3d = Reserved; Don't use
4d = GPIO1 is configured as a PDM clock output (PDMCLK)
5d = Reserved; Don't use
6d = Reserved; Don't use
7d = PD all ADC channels
8d = GPIO1 is configured as an input to control when MICBIAS turns on or off (MICBIAS_EN)
9d = GPIO1 is configured as a general-purpose input (GPI)
10d = GPIO1 is configured as a master clock input (MCLK)
11d = GPIO1 is configured as an ASI input for daisy-chain or ASI input for mixing (SDIN)
12d = GPIO1 is configured as a PDM data input for channel 1 and channel 2 (PDMDIN1)
13d = GPIO1 is configured as a PDM data input for channel 3 and channel 4 (PDMDIN2)
14d to 15d = Reserved; Don't use
3RESERVEDR0bReserved bit; Write only reset value
2-0GPIO1_DRV[2:0]R/W010bGPIO1 output drive configuration.
0d = Hi-Z output
1d = Drive active low and active high
2d = Drive active low and weak high
3d = Drive active low and Hi-Z
4d = Drive weak low and active high
5d = Drive Hi-Z and active high
6d to 7d = Reserved; Don't use

8.6.2.20 GPO_CFG0 Register (Address = 0x22) [Reset = 0x00]

GPO_CFG0 is shown in Table 8-71.

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This registeris the GPO configuration register 0.

Table 8-71 GPO_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7-4GPO1_CFG[3:0]R/W0000bIN2M_GPO1 (GPO1) configuration.
0d = GPO1 is disabled
1d = GPO1 is configured as a general-purpose output (GPO)
2d = GPO1 is configured as a device interrupt output (IRQ)
3d = Reserved; Don't use
4d = GPO1 is configured as a PDM clock output (PDMCLK)
5d to 15d = Reserved; Don't use
3RESERVEDR0bReserved bit; Write only reset value
2-0GPO1_DRV[2:0]R/W000bIN2M_GPO1 (GPO1) output drive configuration.
0d = Hi-Z output
1d = Drive active low and active high
2d = Reserved; Don't use
3d = Drive active low and Hi-Z
4d = Reserved; Don't use
5d = Drive Hi-Z and active high
6d to 7d = Reserved; Don't use

8.6.2.21 GPO_VAL Register (Address = 0x29) [Reset = 0x00]

GPO_VAL is shown in Table 8-72.

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This register is the GPIO and GPO output value register.

Table 8-72 GPO_VAL Register Field Descriptions
BitFieldTypeResetDescription
7GPIO1_VALR/W0bGPIO1 output value when configured as a GPO.
0d = Drive the output with a value of 0
1d = Drive the output with a value of 1
6GPO1_VALR/W0bGPO1 output value when configured as a GPO.
0d = Drive the output with a value of 0
1d = Drive the output with a value of 1
5-0RESERVEDR000000bReserved bits; Write only reset value

8.6.2.22 GPIO_MON Register (Address = 0x2A) [Reset = 0x00]

GPIO_MON is shown in Table 8-73.

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This register is the GPIO monitor value register.

Table 8-73 GPIO_MON Register Field Descriptions
BitFieldTypeResetDescription
7GPIO1_MONR0bGPIO1 monitor value when configured as a GPI.
0d = Input monitor value 0
1d = Input monitor value 1
6-0RESERVEDR0000000bReserved bits; Write only reset value

8.6.2.23 GPI_CFG0 Register (Address = 0x2B) [Reset = 0x00]

GPI_CFG0 is shown in Table 8-74.

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This register is the GPI configuration register 0.

Table 8-74 GPI_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved bit; Write only reset value
6-4GPI1_CFG[2:0]R/W000bIN2P_GPI1 (GPI1) configuration.
0d = GPI1 is disabled
1d = GPI1 is configured as a general-purpose input (GPI)
2d = GPI1 is configured as a master clock input (MCLK)
3d = GPI1 is configured as an ASI input for daisy-chain or ASI input for mixing (SDIN)
4d = GPI1 is configured as a PDM data input for channel 1 and channel 2 (PDMDIN1)
5d = GPI1 is configured as a PDM data input for channel 3 and channel 4 (PDMDIN2)
6d = Reserved; Don't use
7d = PD all ADC channels
3RESERVEDR0bReserved bit; Write only reset value
2-0GPI2_CFG[2:0]R/W000bMICBIAS as GPI2 configuration.
0d = GPI2 is disabled
1d = GPI2 is configured as a general-purpose input (GPI)
2d = GPI2 is configured as a master clock input (MCLK)
3d = GPI2 is configured as an ASI input for daisy-chain or ASI input for mixing (SDIN)
4d = GPI2 is configured as a PDM data input for channel 1 and channel 2 (PDMDIN1)
5d = GPI2 is configured as a PDM data input for channel 3 and channel 4 (PDMDIN2)
6d = Reserved; Don't use
7d = PD all ADC channels

8.6.2.24 GPI_MON Register (Address = 0x2F) [Reset = 0x00]

GPI_MON is shown in Table 8-75.

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This regiser is the GPI monitor value register.

Table 8-75 GPI_MON Register Field Descriptions
BitFieldTypeResetDescription
7GPI1_MONR0bGPI1 monitor value when configured as a GPI.
0d = Input monitor value 0
1d = Input monitor value 1
6GPI2_MONR0bGPI2 monitor value when MICBIAS is configured as a GPI.
0d = Input monitor value 0
1d = Input monitor value 1
5-0RESERVEDR000000bReserved bits; Write only reset value

8.6.2.25 INT_CFG Register (Address = 0x32) [Reset = 0x00]

INT_CFG is shown in Table 8-76.

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This regiser is the interrupt configuration register.

Table 8-76 INT_CFG Register Field Descriptions
BitFieldTypeResetDescription
7INT_POLR/W0bInterrupt polarity.
0d = Active low (IRQZ)
1d = Active high (IRQ)
6-5INT_EVENT[1:0]R/W00bInterrupt event configuration.
0d = INT asserts on any unmasked latched interrupts event
Dont use
2d = INT asserts for 2 ms (typical) for every 4-ms (typical) duration on any unmasked latched interrupts event
3d = INT asserts for 2 ms (typical) one time on each pulse for any unmasked interrupts event
4-3RESERVEDR00bReserved bits; Write only reset value
2LTCH_READ_CFGR/W0bInterrupt latch registers readback configuration.
0d = All interrupts can be read through the LTCH registers
1d = Only unmasked interrupts can be read through the LTCH registers
1-0RESERVEDR00bReserved bits; Write only reset value

8.6.2.26 INT_MASK0 Register (Address = 0x33) [Reset = 0xFF]

INT_MASK0 is shown in Table 8-77.

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This register is the interrupt masks register 0.

Table 8-77 INT_MASK0 Register Field Descriptions
BitFieldTypeResetDescription
7INT_MASK0R/W1bASI clock error mask.
0d = Do not mask
1d = Mask
6INT_MASK0R/W1bPLL Lock interrupt mask.
0d = Do not mask
1d = Mask
5INT_MASK0R/W1bASI input mixing saturation alert mask.
0d = Do not mask
1d = Mask
4INT_MASK0R/W1bVAD Power up detect interrupt mask.
0d = Do not mask
1d = Mask
3INT_MASK0R/W1bVAD Power down detect interrupt mask.
0d = Do not mask
1d = Mask
2RESERVEDR/W1bReserved bit; Write only reset value
1RESERVEDR/W1bReserved bit; Write only reset value
0RESERVEDR/W1bReserved bit; Write only reset value

8.6.2.27 INT_LTCH0 Register (Address = 0x36) [Reset = 0x00]

INT_LTCH0 is shown in Table 8-78.

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This register is the latched Interrupt readback register 0.

Table 8-78 INT_LTCH0 Register Field Descriptions
BitFieldTypeResetDescription
7INT_LTCH0R0bInterrupt caused by an ASI bus clock error (self-clearing bit).
0d = No interrupt
1d = Interrupt
6INT_LTCH0R0bInterrupt caused by PLL LOCK (self-clearing bit).
0d = No interrupt
1d = Interrupt
5INT_LTCH0R0bInterrupt caused by ASI input mixing channel saturation alert (self clearing bit).
0d = No interrupt
1d = Interrupt
4INT_LTCH0R0bInterrupt caused by VAD power up detect (self clearing bit).
0d = No interrupt
1d = Interrupt
3INT_LTCH0R0bInterrupt caused by VAD power down detect (self clearing bit).
0d = No interrupt
1d = Interrupt
2RESERVEDR0bReserved bit; Write only reset value
1RESERVEDR0bReserved bit; Write only reset value
0RESERVEDR0bReserved bit; Write only reset value

8.6.2.28 CM_TOL_CFG Register (Address = 0x3A) [Reset = 0x00]

CM_TOL_CFG is shown in Table 8-79.

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This register is the ADC common mode configuration register

Table 8-79 CM_TOL_CFG Register Field Descriptions
BitFieldTypeResetDescription
7-6CH1_INP_CM_TOL_CFG[1:0]R/W00bChannel 1 input common mode variance tolerance configuration.
0d = Common mode variance tolerance for AC coupled = 100 mVpp and DC coupled = 2.82 Vpp
1d = Common Mode Tolerance of: AC/DC Coupled Input=1V peak to peak
2d = Common Mode Tolerance of: AC/DC Coupled Input=0-AVDD(Supported only with Input Impendance of 10 kΩ/20 kΩ). For input impedance of 2.5 kΩ, input common mode tolerance= 0.4V to 2.6V.
3d = Reserved; Don't use
5-4CH2_INP_CM_TOL_CFG[1:0]R/W00bChannel 2 input common mode variance tolerance configuration.
0d = Common mode variance tolerance for AC coupled = 100 mVpp and DC coupled = 2.82 Vpp
1d = Common Mode Tolerance of: AC/DC Coupled Input=1V peak to peak
2d = Common Mode Tolerance of: AC/DC Coupled Input=0-AVDD(Supported only with Input Impendance of 10 kΩ/20 kΩ). For input impedance of 2.5 kΩ, input common mode tolerance= 0.4V to 2.6V.
3d = Reserved; Don't use
3-0RESERVEDR0000bReserved bits; Write only reset value

8.6.2.29 BIAS_CFG Register (Address = 0x3B) [Reset = 0x00]

BIAS_CFG is shown in Table 8-80.

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This register is the bias and ADC configuration register

Table 8-80 BIAS_CFG Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved bit; Write only reset value
6-4MBIAS_VAL[2:0]R/W000bMICBIAS value.
0d = Microphone bias is set to VREF (2.750 V, 2.500 V, or 1.375 V)
1d = Microphone bias is set to VREF x 1.096 (3.014 V, 2.740 V, or 1.507 V)
2d = Microphone bias is set to VCM = IN1M, for ADC single-ended configuration
3d = Microphone bias is set to VCM = IN2M, for ADC single-ended configuration
4d = Microphone bias is set to VCM = average of IN1M and IN2M, for ADC single-ended configuration
5d = Microphone bias is set to VCM = internal crude common mode
6d = Microphone bias is set to AVDD
7d = MICBIAS configured as GPI2
3-2RESERVEDR00bReserved bits; Write only reset value
1-0ADC_FSCALE[1:0]R/W00bADC full-scale setting (configure this setting based on the AVDD supply minimum voltage used).
0d = VREF is set to 2.75 V to support 2 VRMS for the differential input or 1 VRMS for the single-ended input
1d = VREF is set to 2.5 V to support 1.818 VRMS for the differential input or 0.909 VRMS for the single-ended input
2d = VREF is set to 1.375 V to support 1 VRMS for the differential input or 0.5 VRMS for the single-ended input
3d = Reserved; Don't use

8.6.2.30 CH1_CFG0 Register (Address = 0x3C) [Reset = 0x00]

CH1_CFG0 is shown in Table 8-81.

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This register is configuration register 0 for channel 1.

Table 8-81 CH1_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7CH1_INTYPR/W0bChannel 1 input type.
0d = Microphone input
1d = Line input
6-5CH1_INSRC[1:0]R/W00bChannel 1 input configuration.
0d = Analog differential input
1d = Analog single-ended input
2d = Digital microphone PDM input (configure the GPO and GPI pins accordingly for PDMDIN1 and PDMCLK)
3d = Reserved; Don't use
4CH1_DCR/W0bChannel 1 input coupling (applicable for the analog input).
0d = AC-coupled input
1d = DC-coupled input
3-2CH1_IMP[1:0]R/W00bChannel 1 input impedance (applicable for the analog input).
0d = Typical 2.5-kΩ input impedance
1d = Typical 10-kΩ input impedance
2d = Typical 20-kΩ input impedance
3d = Reserved; Don't use
1RESERVEDR0bReserved bit; Write only reset value
0CH1_AGCENR/W0bChannel 1 automatic gain controller (AGC) setting.
0d = AGC disabled
1d = AGC enabled based on the configuration of bit 3 in register 108 (P0_R108)

8.6.2.31 CH1_CFG1 Register (Address = 0x3D) [Reset = 0x00]

CH1_CFG1 is shown in Table 8-82.

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This register is configuration register 1 for channel 1.

Table 8-82 CH1_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7-1CH1_GAIN[6:0]R/W0000000bChannel 1 gain.
0d = Channel gain is set to 0 dB
1d = Channel gain is set to 0.5 dB
2d = Channel gain is set to 1 dB
3d to 83d = Channel gain is set as per configuration
84d = Channel gain is set to 42 dB
85d to 127d = Reserved; Don't use
0CH1_GAIN_SIGN_BITR/W0bChannel-1 gain sign configuration.
0d = Positive channel gain
1d = Negative channel gain (minimum channel gain supported till -11 dB; supported only for channel input impedance of 10-kΩ and 20-kΩ)

8.6.2.32 CH1_CFG2 Register (Address = 0x3E) [Reset = 0xC9]

CH1_CFG2 is shown in Table 8-83.

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This register is configuration register 2 for channel 1.

Table 8-83 CH1_CFG2 Register Field Descriptions
BitFieldTypeResetDescription
7-0CH1_DVOL[7:0]R/W11001001bChannel 1 digital volume control.
0d = Digital volume is muted
1d = Digital volume control is set to -100 dB
2d = Digital volume control is set to -99.5 dB
3d to 200d = Digital volume control is set as per configuration
201d = Digital volume control is set to 0 dB
202d = Digital volume control is set to 0.5 dB
203d to 253d = Digital volume control is set as per configuration
254d = Digital volume control is set to 26.5 dB
255d = Digital volume control is set to 27 dB

8.6.2.33 CH1_CFG3 Register (Address = 0x3F) [Reset = 0x80]

CH1_CFG3 is shown in Table 8-84.

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This register is configuration register 3 for channel 1.

Table 8-84 CH1_CFG3 Register Field Descriptions
BitFieldTypeResetDescription
7-4CH1_GCAL[3:0]R/W1000bChannel 1 gain calibration.
0d = Gain calibration is set to -0.8 dB
1d = Gain calibration is set to -0.7 dB
2d = Gain calibration is set to -0.6 dB
3d to 7d = Gain calibration is set as per configuration
8d = Gain calibration is set to 0 dB
9d = Gain calibration is set to 0.1 dB
10d to 13d = Gain calibration is set as per configuration
14d = Gain calibration is set to 0.6 dB
15d = Gain calibration is set to 0.7 dB
3-0RESERVEDR0000bReserved bits; Write only reset value

8.6.2.34 CH1_CFG4 Register (Address = 0x40) [Reset = 0x00]

CH1_CFG4 is shown in Table 8-85.

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This register is configuration register 4 for channel 1.

Table 8-85 CH1_CFG4 Register Field Descriptions
BitFieldTypeResetDescription
7-0CH1_PCAL[7:0]R/W00000000bChannel 1 phase calibration with modulator clock resolution.
0d = No phase calibration
1d = Phase calibration delay is set to one cycle of the modulator clock
2d = Phase calibration delay is set to two cycles of the modulator clock
3d to 254d = Phase calibration delay as per configuration
255d = Phase calibration delay is set to 255 cycles of the modulator clock

8.6.2.35 CH2_CFG0 Register (Address = 0x41) [Reset = 0x00]

CH2_CFG0 is shown in Table 8-86.

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This register is configuration register 0 for channel 2.

Table 8-86 CH2_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7CH2_INTYPR/W0bChannel 2 input type.
0d = Microphone input
1d = Line input
6-5CH2_INSRC[1:0]R/W00bChannel 2 input configuration.
0d = Analog differential input (the GPI1 and GPO1 pin functions must be disabled)
1d = Analog single-ended input (the GPI1 and GPO1 pin functions must be disabled)
2d = Digital microphone PDM input (configure the GPO and GPI pins accordingly for PDMDIN1 and PDMCLK)
3d = Reserved; Don't use
4CH2_DCR/W0bChannel 2 input coupling (applicable for the analog input).
0d = AC-coupled input
1d = DC-coupled input
3-2CH2_IMP[1:0]R/W00bChannel 2 input impedance (applicable for the analog input).
0d = Typical 2.5-kΩ input impedance
1d = Typical 10-kΩ input impedance
2d = Typical 20-kΩ input impedance
3d = Reserved; Don't use
1RESERVEDR0bReserved bit; Write only reset value
0CH2_AGCENR/W0bChannel 2 automatic gain controller (AGC) setting.
0d = AGC disabled
1d = AGC enabled based on the configuration of bit 3 in register 108 (P0_R108)

8.6.2.36 CH2_CFG1 Register (Address = 0x42) [Reset = 0x00]

CH2_CFG1 is shown in Table 8-87.

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This register is configuration register 1 for channel 2.

Table 8-87 CH2_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7-1CH2_GAIN[6:0]R/W0000000bChannel 2 gain.
0d = Channel gain is set to 0 dB
1d = Channel gain is set to 0.5 dB
2d = Channel gain is set to 1 dB
3d to 83d = Channel gain is set as per configuration
84d = Channel gain is set to 42 dB
85d to 127d = Reserved; Don't use
0CH2_GAIN_SIGN_BITR/W0bChannel-2 gain sign configuration.
0d = Positive channel gain
1d = Negative channel gain (minimum channel gain supported till -11 dB; supported only for channel input impedance of 10-kΩ and 20-kΩ)

8.6.2.37 CH2_CFG2 Register (Address = 0x43) [Reset = 0xC9]

CH2_CFG2 is shown in Table 8-88.

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This register is configuration register 2 for channel 2.

Table 8-88 CH2_CFG2 Register Field Descriptions
BitFieldTypeResetDescription
7-0CH2_DVOL[7:0]R/W11001001bChannel 2 digital volume control.
0d = Digital volume is muted
1d = Digital volume control is set to -100 dB
2d = Digital volume control is set to -99.5 dB
3d to 200d = Digital volume control is set as per configuration
201d = Digital volume control is set to 0 dB
202d = Digital volume control is set to 0.5 dB
203d to 253d = Digital volume control is set as per configuration
254d = Digital volume control is set to 26.5 dB
255d = Digital volume control is set to 27 dB

8.6.2.38 CH2_CFG3 Register (Address = 0x44) [Reset = 0x80]

CH2_CFG3 is shown in Table 8-89.

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This register is configuration register 3 for channel 2.

Table 8-89 CH2_CFG3 Register Field Descriptions
BitFieldTypeResetDescription
7-4CH2_GCAL[3:0]R/W1000bChannel 2 gain calibration.
0d = Gain calibration is set to -0.8 dB
1d = Gain calibration is set to -0.7 dB
2d = Gain calibration is set to -0.6 dB
3d to 7d = Gain calibration is set as per configuration
8d = Gain calibration is set to 0 dB
9d = Gain calibration is set to 0.1 dB
10d to 13d = Gain calibration is set as per configuration
14d = Gain calibration is set to 0.6 dB
15d = Gain calibration is set to 0.7 dB
3-0RESERVEDR0000bReserved bits; Write only reset value

8.6.2.39 CH2_CFG4 Register (Address = 0x45) [Reset = 0x00]

CH2_CFG4 is shown in Table 8-90.

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This register is configuration register 4 for channel 2.

Table 8-90 CH2_CFG4 Register Field Descriptions
BitFieldTypeResetDescription
7-0CH2_PCAL[7:0]R/W00000000bChannel 2 phase calibration with modulator clock resolution.
0d = No phase calibration
1d = Phase calibration delay is set to one cycle of the modulator clock
2d = Phase calibration delay is set to two cycles of the modulator clock
3d to 254d = Phase calibration delay as per configuration
255d = Phase calibration delay is set to 255 cycles of the modulator clock

8.6.2.40 CH3_CFG2 Register (Address = 0x48) [Reset = 0xC9]

CH3_CFG2 is shown in Table 8-91.

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This register is configuration register 2 for channel 3.

Table 8-91 CH3_CFG2 Register Field Descriptions
BitFieldTypeResetDescription
7-0CH3_DVOL[7:0]R/W11001001bChannel 3 digital volume control.
0d = Digital volume is muted
1d = Digital volume control is set to -100 dB
2d = Digital volume control is set to -99.5 dB
3d to 200d = Digital volume control is set as per configuration
201d = Digital volume control is set to 0 dB
202d = Digital volume control is set to 0.5 dB
203d to 253d = Digital volume control is set as per configuration
254d = Digital volume control is set to 26.5 dB
255d = Digital volume control is set to 27 dB

8.6.2.41 CH3_CFG3 Register (Address = 0x49) [Reset = 0x80]

CH3_CFG3 is shown in Table 8-92.

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This register is configuration register 3 for channel 3.

Table 8-92 CH3_CFG3 Register Field Descriptions
BitFieldTypeResetDescription
7-4CH3_GCAL[3:0]R/W1000bChannel 3 gain calibration.
0d = Gain calibration is set to -0.8 dB
1d = Gain calibration is set to -0.7 dB
2d = Gain calibration is set to -0.6 dB
3d to 7d = Gain calibration is set as per configuration
8d = Gain calibration is set to 0 dB
9d = Gain calibration is set to 0.1 dB
10d to 13d = Gain calibration is set as per configuration
14d = Gain calibration is set to 0.6 dB
15d = Gain calibration is set to 0.7 dB
3-0RESERVEDR0000bReserved bits; Write only reset value

8.6.2.42 CH3_CFG4 Register (Address = 0x4A) [Reset = 0x00]

CH3_CFG4 is shown in Table 8-93.

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This register is configuration register 4 for channel 3.

Table 8-93 CH3_CFG4 Register Field Descriptions
BitFieldTypeResetDescription
7-0CH3_PCAL[7:0]R/W00000000bChannel 3 phase calibration with modulator clock resolution.
0d = No phase calibration
1d = Phase calibration delay is set to one cycle of the modulator clock
2d = Phase calibration delay is set to two cycles of the modulator clock
3d to 254d = Phase calibration delay as per configuration
255d = Phase calibration delay is set to 255 cycles of the modulator clock

8.6.2.43 CH4_CFG2 Register (Address = 0x4D) [Reset = 0xC9]

CH4_CFG2 is shown in Table 8-94.

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This register is configuration register 2 for channel 4.

Table 8-94 CH4_CFG2 Register Field Descriptions
BitFieldTypeResetDescription
7-0CH4_DVOL[7:0]R/W11001001bChannel 4 digital volume control.
0d = Digital volume is muted
1d = Digital volume control is set to -100 dB
2d = Digital volume control is set to -99.5 dB
3d to 200d = Digital volume control is set as per configuration
201d = Digital volume control is set to 0 dB
202d = Digital volume control is set to 0.5 dB
203d to 253d = Digital volume control is set as per configuration
254d = Digital volume control is set to 26.5 dB
255d = Digital volume control is set to 27 dB

8.6.2.44 CH4_CFG3 Register (Address = 0x4E) [Reset = 0x80]

CH4_CFG3 is shown in Table 8-95.

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This register is configuration register 3 for channel 4.

Table 8-95 CH4_CFG3 Register Field Descriptions
BitFieldTypeResetDescription
7-4CH4_GCAL[3:0]R/W1000bChannel 4 gain calibration.
0d = Gain calibration is set to -0.8 dB
1d = Gain calibration is set to -0.7 dB
2d = Gain calibration is set to -0.6 dB
3d to 7d = Gain calibration is set as per configuration
8d = Gain calibration is set to 0 dB
9d = Gain calibration is set to 0.1 dB
10d to 13d = Gain calibration is set as per configuration
14d = Gain calibration is set to 0.6 dB
15d = Gain calibration is set to 0.7 dB
3-0RESERVEDR0000bReserved bits; Write only reset value

8.6.2.45 CH4_CFG4 Register (Address = 0x4F) [Reset = 0x00]

CH4_CFG4 is shown in Table 8-96.

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This register is configuration register 4 for channel 4.

Table 8-96 CH4_CFG4 Register Field Descriptions
BitFieldTypeResetDescription
7-0CH4_PCAL[7:0]R/W00000000bChannel 4 phase calibration with modulator clock resolution.
0d = No phase calibration
1d = Phase calibration delay is set to one cycle of the modulator clock
2d = Phase calibration delay is set to two cycles of the modulator clock
3d to 254d = Phase calibration delay as per configuration
255d = Phase calibration delay is set to 255 cycles of the modulator clock

8.6.2.46 DSP_CFG0 Register (Address = 0x6B) [Reset = 0x01]

DSP_CFG0 is shown in Table 8-97.

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This register is the digital signal processor (DSP) configuration register 0.

Table 8-97 DSP_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7DIS_DVOL_OTF_CHGR/W0bDisable run-time changes to DVOL settings.
0d = Digital volume control changes supported while ADC is powered-on
1d = Digital volume control changes not supported while ADC is powered-on. This is useful for 384 kHz and higher sample rate if more than one channel processing is required.
6RESERVEDR/W0bReserved bit; Write only reset value
5-4DECI_FILT[1:0]R/W00bDecimation filter response.
0d = Linear phase
1d = Low latency
2d = Ultra-low latency
3d = Reserved; Don't use
3-2CH_SUM[1:0]R/W00bChannel summation mode for higher SNR
0d = Channel summation mode is disabled
1d = 2-channel summation mode is enabled to generate a (CH1 + CH2) / 2 output
2d = Reserved; Don't use
3d = Reserved; Don't use
1-0HPF_SEL[1:0]R/W01bHigh-pass filter (HPF) selection.
0d = Programmable first-order IIR filter for a custom HPF with default coefficient values in P4_R72 to P4_R83 set as the all-pass filter
1d = HPF with a cutoff of 0.00025 x fS (12 Hz at fS = 48 kHz) is selected
2d = HPF with a cutoff of 0.002 x fS (96 Hz at fS = 48 kHz) is selected
3d = HPF with a cutoff of 0.008 x fS (384 Hz at fS = 48 kHz) is selected

8.6.2.47 DSP_CFG1 Register (Address = 0x6C) [Reset = 0x40]

DSP_CFG1 is shown in Table 8-98.

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This register is the digital signal processor (DSP) configuration register 1.

Table 8-98 DSP_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7DVOL_GANGR/W0bDVOL control ganged across channels.
0d = Each channel has its own DVOL CTRL settings as programmed in the CHx_DVOL bits
1d = All active channels must use the channel 1 DVOL setting (CH1_DVOL) irrespective of whether channel 1 is turned on or not
6-5BIQUAD_CFG[1:0]R/W10bNumber of biquads per channel configuration.
0d = No biquads per channel; biquads are all disabled
1d = 1 biquad per channel
2d = 2 biquads per channel
3d = 3 biquads per channel
4DISABLE_SOFT_STEPR/W0bSoft-stepping disable during DVOL change, mute, and unmute.
0d = Soft-stepping enabled
1d = Soft-stepping disabled
3AGC_SELR/W0bAGC Selection when is enabled for any channel
0d = AGC is not selected
1d = AGC is selected
2RESERVEDR/W0bReserved bit; Write only reset value
1RESERVEDR/W0bReserved bit; Write only reset value
0EN_AVOID_CLIPR/W0bAnti clippler when channel gain > 0 dB and AGC mode enabled.
0d = Channel gain is maintained as per user programmed value
1d = Signal level is compressed to avoid clipping when channel gain > 0 dB amd signal level crosses programmed threshold setting set in page-4.

8.6.2.48 AGC_CFG0 Register (Address = 0x70) [Reset = 0xE7]

AGC_CFG0 is shown in Table 8-99.

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This register is the automatic gain controller (AGC) configuration register 0.

Table 8-99 AGC_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7-4AGC_LVL[3:0]R/W1110bAGC output signal target level.
0d = Output signal target level is -6 dB
1d = Output signal target level is -8 dB
2d = Output signal target level is -10 dB
3d to 13d = Output signal target level is as per configuration
14d = Output signal target level is -34 dB
15d = Output signal target level is -36 dB
3-0AGC_MAXGAIN[3:0]R/W0111bAGC maximum gain allowed.
0d = Maximum gain allowed is 3 dB
1d = Maximum gain allowed is 6 dB
2d = Maximum gain allowed is 9 dB
3d to 11d = Maximum gain allowed is as per configuration
12d = Maximum gain allowed is 39 dB
13d = Maximum gain allowed is 42 dB
14d to 15d = Reserved; Don't use

8.6.2.49 GAIN_CFG Register (Address = 0x71) [Reset = 0x00]

GAIN_CFG is shown in Table 8-100.

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This register is the channel gain change configuration register.

Table 8-100 GAIN_CFG Register Field Descriptions
BitFieldTypeResetDescription
7-6OTF_GAIN_CHANGE_CFG[1:0]R/W00bOn the fly channel gain change configuration
0d = On-the-fly gain change with some artifacts due to applying gain change immediately
1d = On-the-fly gain change enabled with reduced artifacts but without soft-stepping
2d = On-the-fly gain change enabled with soft-stepping of 0.5 dB per ~20 µs, supported channel gain up to 30 dB for 10-kΩ input impedance mode and 24 dB for 20-kΩ input impedance mode
3d = On-the-fly gain change enabled with soft-stepping of 0.5 dB per ~40 µs, supported channel gain up to 30 dB for 10-kΩ input impedance mode and 24 dB for 20-kΩ input impedance mode
5RESERVEDR/W0bReserved bit; Write only reset value
4-0RESERVEDR00000bReserved bits; Write only reset value

8.6.2.50 IN_CH_EN Register (Address = 0x73) [Reset = 0xC0]

IN_CH_EN is shown in Table 8-101.

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This register is the input channel enable configuration register.

Table 8-101 IN_CH_EN Register Field Descriptions
BitFieldTypeResetDescription
7IN_CH1_ENR/W1bInput channel 1 enable setting.
0d = Channel 1 is disabled
1d = Channel 1 is enabled
6IN_CH2_ENR/W1bInput channel 2 enable setting.
0d = Channel 2 is disabled
1d = Channel 2 is enabled
5IN_CH3_ENR/W0bInput channel 3 (PDM only) enable setting.
0d = Channel 3 is disabled
1d = Channel 3 is enabled
4IN_CH4_ENR/W0bInput channel 4 (PDM only) enable setting.
0d = Channel 4 is disabled
1d = Channel 4 is enabled
3-0RESERVEDR0000bReserved bits; Write only reset value

8.6.2.51 ASI_OUT_CH_EN Register (Address = 0x74) [Reset = 0x00]

ASI_OUT_CH_EN is shown in Table 8-102.

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This register is the ASI output channel enable configuration register.

Table 8-102 ASI_OUT_CH_EN Register Field Descriptions
BitFieldTypeResetDescription
7ASI_OUT_CH1_ENR/W0bASI output channel 1 enable setting.
0d = Channel 1 output slot is in a tri-state condition
1d = Channel 1 output slot is enabled
6ASI_OUT_CH2_ENR/W0bASI output channel 2 enable setting.
0d = Channel 2 output slot is in a tri-state condition
1d = Channel 2 output slot is enabled
5ASI_OUT_CH3_ENR/W0bASI output channel 3 enable setting.
0d = Channel 3 output slot is in a tri-state condition
1d = Channel 3 output slot is enabled
4ASI_OUT_CH4_ENR/W0bASI output channel 4 enable setting.
0d = Channel 4 output slot is in a tri-state condition
1d = Channel 4 output slot is enabled
3-0RESERVEDR0000bReserved bits; Write only reset value

8.6.2.52 PWR_CFG Register (Address = 0x75) [Reset = 0x00]

PWR_CFG is shown in Table 8-103.

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This register is the power-up configuration register.

Table 8-103 PWR_CFG Register Field Descriptions
BitFieldTypeResetDescription
7MICBIAS_PDZR/W0bPower control for MICBIAS.
0d = Power down MICBIAS
1d = Power up MICBIAS
6ADC_PDZR/W0bPower control for ADC and PDM channels.
0d = Power down all ADC and PDM channels
1d = Power up all enabled ADC and PDM channels
5PLL_PDZR/W0bPower control for the PLL.
0d = Power down the PLL
1d = Power up the PLL
4DYN_CH_PUPD_ENR/W0bDynamic channel power-up, power-down enable.
0d = Channel power-up, power-down is not supported if any channel recording is on
1d = Channel can be powered up or down individually, even if channel recording is on
3-2DYN_MAXCH_SEL[1:0]R/W00bDynamic mode maximum channel select configuration.
0d = Channel 1 and channel 2 are used with dynamic channel power-up, power-down feature enabled
1d = Channel 1 to channel 4 are used with dynamic channel power-up, power-down feature enabled
2d = Reserved; Don't use
3d = Reserved; Don't use
1RESERVEDR/W0bReserved bit; Write only reset value
0VAD_ENR/W0bEnable voice activity detection (VAD) algorithm.
0d = VAD is disabled
1d = VAD is enabled

8.6.2.53 DEV_STS0 Register (Address = 0x76) [Reset = 0x00]

DEV_STS0 is shown in Table 8-104.

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This register is the device status value register 0.

Table 8-104 DEV_STS0 Register Field Descriptions
BitFieldTypeResetDescription
7CH1_STATUSR0bADC or PDM channel 1 power status.
0d = ADC or PDM channel is powered down
1d = ADC or PDM channel is powered up
6CH2_STATUSR0bADC or PDM channel 2 power status.
0d = ADC or PDM channel is powered down
1d = ADC or PDM channel is powered up
5-0RESERVEDR000000bReserved bits; Write only reset value

8.6.2.54 DEV_STS1 Register (Address = 0x77) [Reset = 0x80]

DEV_STS1 is shown in Table 8-105.

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This register is the device status value register 1.

Table 8-105 DEV_STS1 Register Field Descriptions
BitFieldTypeResetDescription
7-5MODE_STS[2:0]R100bDevice mode status.
4d = Device is in sleep mode or software shutdown mode
6d = Device is in active mode with all ADC or PDM channels turned off
7d = Device is in active mode with at least one ADC or PDM channel turned on
4-0RESERVEDR00000bReserved bits; Write only reset value

8.6.2.55 I2C_CKSUM Register (Address = 0x7E) [Reset = 0x00]

I2C_CKSUM is shown in Table 8-106.

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This register returns the I2C transactions checksum value.

Table 8-106 I2C_CKSUM Register Field Descriptions
BitFieldTypeResetDescription
7-0I2C_CKSUM[7:0]R/W00000000bThese bits return the I2C transactions checksum value. Writing to this register resets the checksum to the written value. This register is updated on writes to other registers on all pages.