This register is the digital signal processor (DSP) configuration register 0.
|5-4||DECI_FILT[1:0]||RW||0h||Decimation filter response.
0d = Linear phase
1d = Low latency
2d = Ultra-low latency
|3-2||CH_SUM[1:0]||RW||0h||Channel summation mode for higher SNR
0d = Channel summation mode is disabled
1d = 2-channel summation mode is enabled to generate a (CH1 + CH2) / 2 and a (CH3 + CH4) / 2 output
2d = 4-channel summation mode is enabled to generate a (CH1 + CH2 + CH3 + CH4) / 4 output
3d = Reserved
|1-0||HPF_SEL[1:0]||RW||1h||High-pass filter (HPF) selection.
0d = Programmable first-order IIR filter for a custom HPF with default coefficient values in P4_R72 to P4_R83 set as the all-pass filter
1d = HPF with a cutoff of 0.00025 x fS (12 Hz at fS = 48 kHz) is selected
2d = HPF with a cutoff of 0.002 x fS (96 Hz at fS = 48 kHz) is selected
3d = HPF with a cutoff of 0.008 x fS (384 Hz at fS = 48 kHz) is selected