SBAS884A March   2020  – June 2020 PCM6240-Q1 , PCM6260-Q1 , PCM6340-Q1 , PCM6360-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Application Diagram (PCM6260-Q1)
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions: PCM6240-Q1
    2.     Pin Functions: PCM6260-Q1
    3.     Pin Functions: PCM6340-Q1
    4.     Pin Functions: PCM6360-Q1
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements: I2C Interface
    7. 7.7  Switching Characteristics: I2C Interface
    8. 7.8  Timing Requirements: SPI Interface
    9. 7.9  Switching Characteristics: SPI Interface
    10. 7.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 7.11 Switching Characteristics: TDM, I2S or LJ Interface
    12. 7.12 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Serial Interfaces
        1. 8.3.1.1 Control Serial Interfaces
        2. 8.3.1.2 Audio Serial Interfaces
          1. 8.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 8.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 8.3.1.2.3 Left-Justified (LJ) Interface
        3. 8.3.1.3 Using Multiple Devices With Shared Buses
      2. 8.3.2 Phase-Locked Loop (PLL) and Clock Generation
      3. 8.3.3 Input Channel Configuration
      4. 8.3.4 Reference Voltage
      5. 8.3.5 Microphone Bias
      6. 8.3.6 Input DC Fault Diagnostics
        1. 8.3.6.1 Fault Conditions
          1. 8.3.6.1.1 Input Pin Short to Ground
          2. 8.3.6.1.2 Input Pin Short to MICBIAS
          3. 8.3.6.1.3 Open Inputs
          4. 8.3.6.1.4 Short Between INxP and INxM
          5. 8.3.6.1.5 Input Pin Overvoltage
          6. 8.3.6.1.6 Input Pin Short to VBAT_IN
        2. 8.3.6.2 Fault Reporting
          1. 8.3.6.2.1 Overcurrent and Overtemperature Protection
      7. 8.3.7 Signal-Chain Processing
        1. 8.3.7.1 Programmable Channel Gain and Digital Volume Control
        2. 8.3.7.2 Programmable Channel Gain Calibration
        3. 8.3.7.3 Programmable Channel Phase Calibration
        4. 8.3.7.4 Programmable Digital High-Pass Filter
        5. 8.3.7.5 Programmable Digital Biquad Filters
        6. 8.3.7.6 Programmable Channel Summer and Digital Mixer
        7. 8.3.7.7 Configurable Digital Decimation Filters
          1. 8.3.7.7.1 Linear Phase Filters
            1. 8.3.7.7.1.1 Sampling Rate: 8 kHz or 7.35 kHz
            2. 8.3.7.7.1.2 Sampling Rate: 16 kHz or 14.7 kHz
            3. 8.3.7.7.1.3 Sampling Rate: 24 kHz or 22.05 kHz
            4. 8.3.7.7.1.4 Sampling Rate: 32 kHz or 29.4 kHz
            5. 8.3.7.7.1.5 Sampling Rate: 48 kHz or 44.1 kHz
            6. 8.3.7.7.1.6 Sampling Rate: 96 kHz or 88.2 kHz
            7. 8.3.7.7.1.7 Sampling Rate: 192 kHz or 176.4 kHz
            8. 8.3.7.7.1.8 Sampling Rate: 384 kHz or 352.8 kHz
            9. 8.3.7.7.1.9 Sampling Rate: 768 kHz or 705.6 kHz
          2. 8.3.7.7.2 Low-Latency Filters
            1. 8.3.7.7.2.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 8.3.7.7.2.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 8.3.7.7.2.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 8.3.7.7.2.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 8.3.7.7.2.5 Sampling Rate: 96 kHz or 88.2 kHz
            6. 8.3.7.7.2.6 Sampling Rate: 192 kHz or 176.4 kHz
          3. 8.3.7.7.3 Ultra-Low-Latency Filters
            1. 8.3.7.7.3.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 8.3.7.7.3.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 8.3.7.7.3.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 8.3.7.7.3.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 8.3.7.7.3.5 Sampling Rate: 96 kHz or 88.2 kHz
            6. 8.3.7.7.3.6 Sampling Rate: 192 kHz or 176.4 kHz
            7. 8.3.7.7.3.7 Sampling Rate: 384 kHz or 352.8 kHz
      8. 8.3.8 Automatic Gain Controller (AGC)
      9. 8.3.9 Interrupts, Status, and Digital I/O Pin Multiplexing
    4. 8.4 Device Functional Modes
      1. 8.4.1 Hardware Shutdown
      2. 8.4.2 Sleep Mode or Software Shutdown
      3. 8.4.3 Active Mode
      4. 8.4.4 Software Reset
    5. 8.5 Programming
      1. 8.5.1 Control Serial Interfaces
        1. 8.5.1.1 I2C Control Interface
          1. 8.5.1.1.1 General I2C Operation
          2. 8.5.1.1.2 I2C Single-Byte and Multiple-Byte Transfers
            1. 8.5.1.1.2.1 I2C Single-Byte Write
            2. 8.5.1.1.2.2 I2C Multiple-Byte Write
            3. 8.5.1.1.2.3 I2C Single-Byte Read
            4. 8.5.1.1.2.4 I2C Multiple-Byte Read
        2. 8.5.1.2 SPI Control Interface
          1. Table 1. SPI Command Word
    6. 8.6 Register Maps
      1. 8.6.1 Device Configuration Registers
        1. 8.6.1.1 Register Summary Table Page=0x00
        2. 8.6.1.2 Register Summary Table Page=0x01
        3. 8.6.1.3 Register Description: Page = 0x00
          1. 8.6.1.3.1  PAGE_CFG Register (page = 0x00, address = 0x00) [reset = 0h]
            1. Table 51. PAGE_CFG Register Field Descriptions
          2. 8.6.1.3.2  SW_RESET Register (page = 0x00, address = 0x01) [reset = 0h]
            1. Table 52. SW_RESET Register Field Descriptions
          3. 8.6.1.3.3  SLEEP_CFG Register (page = 0x00, address = 0x02) [reset = 0h]
            1. Table 53. SLEEP_CFG Register Field Descriptions
          4. 8.6.1.3.4  SHDN_CFG Register (page = 0x00, address = 0x05) [reset = 5h]
            1. Table 54. SHDN_CFG Register Field Descriptions
          5. 8.6.1.3.5  ASI_CFG0 Register (page = 0x00, address = 0x07) [reset = 30h]
            1. Table 55. ASI_CFG0 Register Field Descriptions
          6. 8.6.1.3.6  ASI_CFG1 Register (page = 0x00, address = 0x08) [reset = 0h]
            1. Table 56. ASI_CFG1 Register Field Descriptions
          7. 8.6.1.3.7  ASI_CFG2 Register (page = 0x00, address = 0x09) [reset = 0h]
            1. Table 57. ASI_CFG2 Register Field Descriptions
          8. 8.6.1.3.8  ASI_CH1 Register (page = 0x00, address = 0x0B) [reset = 0h]
            1. Table 58. ASI_CH1 Register Field Descriptions
          9. 8.6.1.3.9  ASI_CH2 Register (page = 0x00, address = 0x0C) [reset = 1h]
            1. Table 59. ASI_CH2 Register Field Descriptions
          10. 8.6.1.3.10 ASI_CH3 Register (page = 0x00, address = 0x0D) [reset = 2h]
            1. Table 60. ASI_CH3 Register Field Descriptions
          11. 8.6.1.3.11 ASI_CH4 Register (page = 0x00, address = 0x0E) [reset = 3h]
            1. Table 61. ASI_CH4 Register Field Descriptions
          12. 8.6.1.3.12 ASI_CH5 Register (page = 0x00, address = 0x0F) [reset = 4h]
            1. Table 62. ASI_CH5 Register Field Descriptions
          13. 8.6.1.3.13 ASI_CH6 Register (page = 0x00, address = 0x10) [reset = 5h]
            1. Table 63. ASI_CH6 Register Field Descriptions
          14. 8.6.1.3.14 MST_CFG0 Register (page = 0x00, address = 0x13) [reset = 2h]
            1. Table 64. MST_CFG0 Register Field Descriptions
          15. 8.6.1.3.15 MST_CFG1 Register (page = 0x00, address = 0x14) [reset = 48h]
            1. Table 65. MST_CFG1 Register Field Descriptions
          16. 8.6.1.3.16 ASI_STS Register (page = 0x00, address = 0x15) [reset = FFh]
            1. Table 66. ASI_STS Register Field Descriptions
          17. 8.6.1.3.17 CLK_SRC Register (page = 0x00, address = 0x16) [reset = 10h]
            1. Table 67. CLK_SRC Register Field Descriptions
          18. 8.6.1.3.18 GPIO_CFG0 Register (page = 0x00, address = 0x21) [reset = 22h]
            1. Table 68. GPIO_CFG0 Register Field Descriptions
          19. 8.6.1.3.19 GPIO_CFG1 Register (page = 0x00, address = 0x22) [reset = 0h]
            1. Table 69. GPIO_CFG1 Register Field Descriptions
          20. 8.6.1.3.20 GPIO_CFG2 Register (page = 0x00, address = 0x23) [reset = 0h]
            1. Table 70. GPIO_CFG2 Register Field Descriptions
          21. 8.6.1.3.21 GPI_CFG0 Register (page = 0x00, address = 0x24) [reset = 0h]
            1. Table 71. GPI_CFG0 Register Field Descriptions
          22. 8.6.1.3.22 GPI_CFG1 Register (page = 0x00, address = 0x25) [reset = 0h]
            1. Table 72. GPI_CFG1 Register Field Descriptions
          23. 8.6.1.3.23 GPIO_VAL Register (page = 0x00, address = 0x26) [reset = 0h]
            1. Table 73. GPIO_VAL Register Field Descriptions
          24. 8.6.1.3.24 GPIO_MON Register (page = 0x00, address = 0x27) [reset = 0h]
            1. Table 74. GPIO_MON Register Field Descriptions
          25. 8.6.1.3.25 INT_CFG Register (page = 0x00, address = 0x28) [reset = 0h]
            1. Table 75. INT_CFG Register Field Descriptions
          26. 8.6.1.3.26 INT_MASK0 Register (page = 0x00, address = 0x29) [reset = FFh]
            1. Table 76. INT_MASK0 Register Field Descriptions
          27. 8.6.1.3.27 INT_MASK1 Register (page = 0x00, address = 0x2A) [reset = 3h]
            1. Table 77. INT_MASK1 Register Field Descriptions
          28. 8.6.1.3.28 INT_MASK2 Register (page = 0x00, address = 0x2B) [reset = 0h]
            1. Table 78. INT_MASK2 Register Field Descriptions
          29. 8.6.1.3.29 INT_LTCH0 Register (page = 0x00, address = 0x2C) [reset = 0h]
            1. Table 79. INT_LTCH0 Register Field Descriptions
          30. 8.6.1.3.30 CHx_LTCH Register (page = 0x00, address = 0x2D) [reset = 0h]
            1. Table 80. CHx_LTCH Register Field Descriptions
          31. 8.6.1.3.31 CH1_LTCH Register (page = 0x00, address = 0x2E) [reset = 0h]
            1. Table 81. CH1_LTCH Register Field Descriptions
          32. 8.6.1.3.32 CH2_LTCH Register (page = 0x00, address = 0x2F) [reset = 0h]
            1. Table 82. CH2_LTCH Register Field Descriptions
          33. 8.6.1.3.33 CH3_LTCH Register (page = 0x00, address = 0x30) [reset = 0h]
            1. Table 83. CH3_LTCH Register Field Descriptions
          34. 8.6.1.3.34 CH4_LTCH Register (page = 0x00, address = 0x31) [reset = 0h]
            1. Table 84. CH4_LTCH Register Field Descriptions
          35. 8.6.1.3.35 CH5_LTCH Register (page = 0x00, address = 0x32) [reset = 0h]
            1. Table 85. CH5_LTCH Register Field Descriptions
          36. 8.6.1.3.36 CH6_LTCH Register (page = 0x00, address = 0x33) [reset = 0h]
            1. Table 86. CH6_LTCH Register Field Descriptions
          37. 8.6.1.3.37 INT_MASK3 Register (page = 0x00, address = 0x34) [reset = 0h]
            1. Table 87. INT_MASK3 Register Field Descriptions
          38. 8.6.1.3.38 INT_LTCH1 Register (page = 0x00, address = 0x35) [reset = 0h]
            1. Table 88. INT_LTCH1 Register Field Descriptions
          39. 8.6.1.3.39 INT_LTCH2 Register (page = 0x00, address = 0x36) [reset = 0h]
            1. Table 89. INT_LTCH2 Register Field Descriptions
          40. 8.6.1.3.40 INT_LTCH3 Register (page = 0x00, address = 0x37) [reset = 0h]
            1. Table 90. INT_LTCH3 Register Field Descriptions
          41. 8.6.1.3.41 MBDIAG_CFG0 Register (page = 0x00, address = 0x38) [reset = BAh]
            1. Table 91. MBDIAG_CFG0 Register Field Descriptions
          42. 8.6.1.3.42 MBDIAG_CFG1 Register (page = 0x00, address = 0x39) [reset = 4Bh]
            1. Table 92. MBDIAG_CFG1 Register Field Descriptions
          43. 8.6.1.3.43 MBDIAG_CFG2 Register (page = 0x00, address = 0x3A) [reset = 10h]
            1. Table 93. MBDIAG_CFG2 Register Field Descriptions
          44. 8.6.1.3.44 BIAS_CFG Register (page = 0x00, address = 0x3B) [reset = D0h]
            1. Table 94. BIAS_CFG Register Field Descriptions
          45. 8.6.1.3.45 CH1_CFG0 Register (page = 0x00, address = 0x3C) [reset = 10h]
            1. Table 95. CH1_CFG0 Register Field Descriptions
          46. 8.6.1.3.46 CH1_CFG1 Register (page = 0x00, address = 0x3D) [reset = 0h]
            1. Table 96. CH1_CFG1 Register Field Descriptions
          47. 8.6.1.3.47 CH1_CFG2 Register (page = 0x00, address = 0x3E) [reset = C9h]
            1. Table 97. CH1_CFG2 Register Field Descriptions
          48. 8.6.1.3.48 CH1_CFG3 Register (page = 0x00, address = 0x3F) [reset = 80h]
            1. Table 98. CH1_CFG3 Register Field Descriptions
          49. 8.6.1.3.49 CH1_CFG4 Register (page = 0x00, address = 0x40) [reset = 0h]
            1. Table 99. CH1_CFG4 Register Field Descriptions
          50. 8.6.1.3.50 CH2_CFG0 Register (page = 0x00, address = 0x41) [reset = 10h]
            1. Table 100. CH2_CFG0 Register Field Descriptions
          51. 8.6.1.3.51 CH2_CFG1 Register (page = 0x00, address = 0x42) [reset = 0h]
            1. Table 101. CH2_CFG1 Register Field Descriptions
          52. 8.6.1.3.52 CH2_CFG2 Register (page = 0x00, address = 0x43) [reset = C9h]
            1. Table 102. CH2_CFG2 Register Field Descriptions
          53. 8.6.1.3.53 CH2_CFG3 Register (page = 0x00, address = 0x44) [reset = 80h]
            1. Table 103. CH2_CFG3 Register Field Descriptions
          54. 8.6.1.3.54 CH2_CFG4 Register (page = 0x00, address = 0x45) [reset = 0h]
            1. Table 104. CH2_CFG4 Register Field Descriptions
          55. 8.6.1.3.55 CH3_CFG0 Register (page = 0x00, address = 0x46) [reset = 10h]
            1. Table 105. CH3_CFG0 Register Field Descriptions
          56. 8.6.1.3.56 CH3_CFG1 Register (page = 0x00, address = 0x47) [reset = 0h]
            1. Table 106. CH3_CFG1 Register Field Descriptions
          57. 8.6.1.3.57 CH3_CFG2 Register (page = 0x00, address = 0x48) [reset = C9h]
            1. Table 107. CH3_CFG2 Register Field Descriptions
          58. 8.6.1.3.58 CH3_CFG3 Register (page = 0x00, address = 0x49) [reset = 80h]
            1. Table 108. CH3_CFG3 Register Field Descriptions
          59. 8.6.1.3.59 CH3_CFG4 Register (page = 0x00, address = 0x4A) [reset = 0h]
            1. Table 109. CH3_CFG4 Register Field Descriptions
          60. 8.6.1.3.60 CH4_CFG0 Register (page = 0x00, address = 0x4B) [reset = 10h]
            1. Table 110. CH4_CFG0 Register Field Descriptions
          61. 8.6.1.3.61 CH4_CFG1 Register (page = 0x00, address = 0x4C) [reset = 0h]
            1. Table 111. CH4_CFG1 Register Field Descriptions
          62. 8.6.1.3.62 CH4_CFG2 Register (page = 0x00, address = 0x4D) [reset = C9h]
            1. Table 112. CH4_CFG2 Register Field Descriptions
          63. 8.6.1.3.63 CH4_CFG3 Register (page = 0x00, address = 0x4E) [reset = 80h]
            1. Table 113. CH4_CFG3 Register Field Descriptions
          64. 8.6.1.3.64 CH4_CFG4 Register (page = 0x00, address = 0x4F) [reset = 0h]
            1. Table 114. CH4_CFG4 Register Field Descriptions
          65. 8.6.1.3.65 CH5_CFG0 Register (page = 0x00, address = 0x50) [reset = 10h]
            1. Table 115. CH5_CFG0 Register Field Descriptions
          66. 8.6.1.3.66 CH5_CFG1 Register (page = 0x00, address = 0x51) [reset = 0h]
            1. Table 116. CH5_CFG1 Register Field Descriptions
          67. 8.6.1.3.67 CH5_CFG2 Register (page = 0x00, address = 0x52) [reset = C9h]
            1. Table 117. CH5_CFG2 Register Field Descriptions
          68. 8.6.1.3.68 CH5_CFG3 Register (page = 0x00, address = 0x53) [reset = 80h]
            1. Table 118. CH5_CFG3 Register Field Descriptions
          69. 8.6.1.3.69 CH5_CFG4 Register (page = 0x00, address = 0x54) [reset = 0h]
            1. Table 119. CH5_CFG4 Register Field Descriptions
          70. 8.6.1.3.70 CH6_CFG0 Register (page = 0x00, address = 0x55) [reset = 10h]
            1. Table 120. CH6_CFG0 Register Field Descriptions
          71. 8.6.1.3.71 CH6_CFG1 Register (page = 0x00, address = 0x56) [reset = 0h]
            1. Table 121. CH6_CFG1 Register Field Descriptions
          72. 8.6.1.3.72 CH6_CFG2 Register (page = 0x00, address = 0x57) [reset = C9h]
            1. Table 122. CH6_CFG2 Register Field Descriptions
          73. 8.6.1.3.73 CH6_CFG3 Register (page = 0x00, address = 0x58) [reset = 80h]
            1. Table 123. CH6_CFG3 Register Field Descriptions
          74. 8.6.1.3.74 CH6_CFG4 Register (page = 0x00, address = 0x59) [reset = 0h]
            1. Table 124. CH6_CFG4 Register Field Descriptions
          75. 8.6.1.3.75 DIAG_CFG0 Register (page = 0x00, address = 0x64) [reset = 0h]
            1. Table 125. DIAG_CFG0 Register Field Descriptions
          76. 8.6.1.3.76 DIAG_CFG1 Register (page = 0x00, address = 0x65) [reset = 37h]
            1. Table 126. DIAG_CFG1 Register Field Descriptions
          77. 8.6.1.3.77 DIAG_CFG2 Register (page = 0x00, address = 0x66) [reset = 87h]
            1. Table 127. DIAG_CFG2 Register Field Descriptions
          78. 8.6.1.3.78 DIAG_CFG3 Register (page = 0x00, address = 0x67) [reset = B8h]
            1. Table 128. DIAG_CFG3 Register Field Descriptions
          79. 8.6.1.3.79 DIAG_CFG4 Register (page = 0x00, address = 0x68) [reset = 0h]
            1. Table 129. DIAG_CFG4 Register Field Descriptions
          80. 8.6.1.3.80 DSP_CFG0 Register (page = 0x00, address = 0x6B) [reset = 1h]
            1. Table 130. DSP_CFG0 Register Field Descriptions
          81. 8.6.1.3.81 DSP_CFG1 Register (page = 0x00, address = 0x6C) [reset = 48h]
            1. Table 131. DSP_CFG1 Register Field Descriptions
          82. 8.6.1.3.82 AGC_CFG0 Register (page = 0x00, address = 0x70) [reset = E7h]
            1. Table 132. AGC_CFG0 Register Field Descriptions
          83. 8.6.1.3.83 IN_CH_EN Register (page = 0x00, address = 0x73) [reset = FCh]
            1. Table 133. IN_CH_EN Register Field Descriptions
          84. 8.6.1.3.84 ASI_OUT_CH_EN Register (page = 0x00, address = 0x74) [reset = 0h]
            1. Table 134. ASI_OUT_CH_EN Register Field Descriptions
          85. 8.6.1.3.85 PWR_CFG Register (page = 0x00, address = 0x75) [reset = 0h]
            1. Table 135. PWR_CFG Register Field Descriptions
          86. 8.6.1.3.86 DEV_STS0 Register (page = 0x00, address = 0x76) [reset = 0h]
            1. Table 136. DEV_STS0 Register Field Descriptions
          87. 8.6.1.3.87 DEV_STS1 Register (page = 0x00, address = 0x77) [reset = 80h]
            1. Table 137. DEV_STS1 Register Field Descriptions
          88. 8.6.1.3.88 I2C_CKSUM Register (page = 0x00, address = 0x7E) [reset = 0h]
            1. Table 138. I2C_CKSUM Register Field Descriptions
        4. 8.6.1.4 Register Description: Page = 0x01
          1. 8.6.1.4.1  PAGE_CFG Register (page = 0x01, address = 0x00) [reset = 0h]
            1. Table 139. PAGE_CFG Register Field Descriptions
          2. 8.6.1.4.2  MBIAS_LOAD Register (page = 0x01, address = 0x16) [reset = 0h]
            1. Table 140. MBIAS_LOAD Register Field Descriptions
          3. 8.6.1.4.3  INT_LIVE0 Register (page = 0x01, address = 0x2C) [reset = 0h]
            1. Table 141. INT_LIVE0 Register Field Descriptions
          4. 8.6.1.4.4  CHx_LIVE Register (page = 0x01, address = 0x2D) [reset = 0h]
            1. Table 142. CHx_LIVE Register Field Descriptions
          5. 8.6.1.4.5  CH1_LIVE Register (page = 0x01, address = 0x2E) [reset = 0h]
            1. Table 143. CH1_LIVE Register Field Descriptions
          6. 8.6.1.4.6  CH2_LIVE Register (page = 0x01, address = 0x2F) [reset = 0h]
            1. Table 144. CH2_LIVE Register Field Descriptions
          7. 8.6.1.4.7  CH3_LIVE Register (page = 0x01, address = 0x30) [reset = 0h]
            1. Table 145. CH3_LIVE Register Field Descriptions
          8. 8.6.1.4.8  CH4_LIVE Register (page = 0x01, address = 0x31) [reset = 0h]
            1. Table 146. CH4_LIVE Register Field Descriptions
          9. 8.6.1.4.9  CH5_LIVE Register (page = 0x01, address = 0x32) [reset = 0h]
            1. Table 147. CH5_LIVE Register Field Descriptions
          10. 8.6.1.4.10 CH6_LIVE Register (page = 0x01, address = 0x33) [reset = 0h]
            1. Table 148. CH6_LIVE Register Field Descriptions
          11. 8.6.1.4.11 INT_LIVE1 Register (page = 0x01, address = 0x35) [reset = 0h]
            1. Table 149. INT_LIVE1 Register Field Descriptions
          12. 8.6.1.4.12 INT_LIVE3 Register (page = 0x01, address = 0x37) [reset = 0h]
            1. Table 150. INT_LIVE3 Register Field Descriptions
          13. 8.6.1.4.13 MBIAS_OV_CFG Register (page = 0x01, address = 0x55) [reset = 40h]
            1. Table 151. MBIAS_OV_CFG Register Field Descriptions
          14. 8.6.1.4.14 DIAGDATA_CFG Register (page = 0x01, address = 0x59) [reset = 0h]
            1. Table 152. DIAGDATA_CFG Register Field Descriptions
          15. 8.6.1.4.15 DIAG_MON_MSB_VBAT Register (page = 0x01, address = 0x5A) [reset = 0h]
            1. Table 153. DIAG_MON_MSB_VBAT Register Field Descriptions
          16. 8.6.1.4.16 DIAG_MON_LSB_VBAT Register (page = 0x01, address = 0x5B) [reset = 0h]
            1. Table 154. DIAG_MON_LSB_VBAT Register Field Descriptions
          17. 8.6.1.4.17 DIAG_MON_MSB_MBIAS Register (page = 0x01, address = 0x5C) [reset = 0h]
            1. Table 155. DIAG_MON_MSB_MBIAS Register Field Descriptions
          18. 8.6.1.4.18 DIAG_MON_LSB_MBIAS Register (page = 0x01, address = 0x5D) [reset = 1h]
            1. Table 156. DIAG_MON_LSB_MBIAS Register Field Descriptions
          19. 8.6.1.4.19 DIAG_MON_MSB_IN1P Register (page = 0x01, address = 0x5E) [reset = 0h]
            1. Table 157. DIAG_MON_MSB_IN1P Register Field Descriptions
          20. 8.6.1.4.20 DIAG_MON_LSB_IN1P Register (page = 0x01, address = 0x5F) [reset = 2h]
            1. Table 158. DIAG_MON_LSB_IN1P Register Field Descriptions
          21. 8.6.1.4.21 DIAG_MON_MSB_IN1M Register (page = 0x01, address = 0x60) [reset = 0h]
            1. Table 159. DIAG_MON_MSB_IN1M Register Field Descriptions
          22. 8.6.1.4.22 DIAG_MON_LSB_IN1M Register (page = 0x01, address = 0x61) [reset = 3h]
            1. Table 160. DIAG_MON_LSB_IN1M Register Field Descriptions
          23. 8.6.1.4.23 DIAG_MON_MSB_IN2P Register (page = 0x01, address = 0x62) [reset = 0h]
            1. Table 161. DIAG_MON_MSB_IN2P Register Field Descriptions
          24. 8.6.1.4.24 DIAG_MON_LSB_IN2P Register (page = 0x01, address = 0x63) [reset = 4h]
            1. Table 162. DIAG_MON_LSB_IN2P Register Field Descriptions
          25. 8.6.1.4.25 DIAG_MON_MSB_IN2M Register (page = 0x01, address = 0x64) [reset = 0h]
            1. Table 163. DIAG_MON_MSB_IN2M Register Field Descriptions
          26. 8.6.1.4.26 DIAG_MON_LSB_IN2M Register (page = 0x01, address = 0x65) [reset = 5h]
            1. Table 164. DIAG_MON_LSB_IN2M Register Field Descriptions
          27. 8.6.1.4.27 DIAG_MON_MSB_IN3P Register (page = 0x01, address = 0x66) [reset = 0h]
            1. Table 165. DIAG_MON_MSB_IN3P Register Field Descriptions
          28. 8.6.1.4.28 DIAG_MON_LSB_IN3P Register (page = 0x01, address = 0x67) [reset = 6h]
            1. Table 166. DIAG_MON_LSB_IN3P Register Field Descriptions
          29. 8.6.1.4.29 DIAG_MON_MSB_IN3M Register (page = 0x01, address = 0x68) [reset = 0h]
            1. Table 167. DIAG_MON_MSB_IN3M Register Field Descriptions
          30. 8.6.1.4.30 DIAG_MON_LSB_IN3M Register (page = 0x01, address = 0x69) [reset = 7h]
            1. Table 168. DIAG_MON_LSB_IN3M Register Field Descriptions
          31. 8.6.1.4.31 DIAG_MON_MSB_IN4P Register (page = 0x01, address = 0x6A) [reset = 0h]
            1. Table 169. DIAG_MON_MSB_IN4P Register Field Descriptions
          32. 8.6.1.4.32 DIAG_MON_LSB_IN4P Register (page = 0x01, address = 0x6B) [reset = 8h]
            1. Table 170. DIAG_MON_LSB_IN4P Register Field Descriptions
          33. 8.6.1.4.33 DIAG_MON_MSB_IN4M Register (page = 0x01, address = 0x6C) [reset = 0h]
            1. Table 171. DIAG_MON_MSB_IN4M Register Field Descriptions
          34. 8.6.1.4.34 DIAG_MON_LSB_IN4M Register (page = 0x01, address = 0x6D) [reset = 9h]
            1. Table 172. DIAG_MON_LSB_IN4M Register Field Descriptions
          35. 8.6.1.4.35 DIAG_MON_MSB_IN5P Register (page = 0x01, address = 0x6E) [reset = 0h]
            1. Table 173. DIAG_MON_MSB_IN5P Register Field Descriptions
          36. 8.6.1.4.36 DIAG_MON_LSB_IN5P Register (page = 0x01, address = 0x6F) [reset = Ah]
            1. Table 174. DIAG_MON_LSB_IN5P Register Field Descriptions
          37. 8.6.1.4.37 DIAG_MON_MSB_IN5M Register (page = 0x01, address = 0x70) [reset = 0h]
            1. Table 175. DIAG_MON_MSB_IN5M Register Field Descriptions
          38. 8.6.1.4.38 DIAG_MON_LSB_IN5M Register (page = 0x01, address = 0x71) [reset = Bh]
            1. Table 176. DIAG_MON_LSB_IN5M Register Field Descriptions
          39. 8.6.1.4.39 DIAG_MON_MSB_IN6P Register (page = 0x01, address = 0x72) [reset = 0h]
            1. Table 177. DIAG_MON_MSB_IN6P Register Field Descriptions
          40. 8.6.1.4.40 DIAG_MON_LSB_IN6P Register (page = 0x01, address = 0x73) [reset = Ch]
            1. Table 178. DIAG_MON_LSB_IN6P Register Field Descriptions
          41. 8.6.1.4.41 DIAG_MON_MSB_IN6M Register (page = 0x01, address = 0x74) [reset = 0h]
            1. Table 179. DIAG_MON_MSB_IN6M Register Field Descriptions
          42. 8.6.1.4.42 DIAG_MON_LSB_IN6M Register (page = 0x01, address = 0x75) [reset = Dh]
            1. Table 180. DIAG_MON_LSB_IN6M Register Field Descriptions
          43. 8.6.1.4.43 DIAG_MON_MSB_TEMP Register (page = 0x01, address = 0x76) [reset = 0h]
            1. Table 181. DIAG_MON_MSB_TEMP Register Field Descriptions
          44. 8.6.1.4.44 DIAG_MON_LSB_TEMP Register (page = 0x01, address = 0x77) [reset = Eh]
            1. Table 182. DIAG_MON_LSB_TEMP Register Field Descriptions
          45. 8.6.1.4.45 DIAG_MON_MSB_LOAD Register (page = 0x01, address = 0x78) [reset = 0h]
            1. Table 183. DIAG_MON_MSB_LOAD Register Field Descriptions
          46. 8.6.1.4.46 DIAG_MON_LSB_LOAD Register (page = 0x01, address = 0x79) [reset = Fh]
            1. Table 184. DIAG_MON_LSB_LOAD Register Field Descriptions
      2. 8.6.2 Programmable Coefficient Registers
        1. 8.6.2.1 Programmable Coefficient Registers: Page = 0x02
        2. 8.6.2.2 Programmable Coefficient Registers: Page = 0x03
        3. 8.6.2.3 Programmable Coefficient Registers: Page = 0x04
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Four-Channel Analog Microphone Recording Using the PCM6240-Q1
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Example Device Register Configuration Script for EVM Setup
        3. 9.2.1.3 Application Curves
    3. 9.3 What To Do and What Not To Do
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Support Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.9 Interrupts, Status, and Digital I/O Pin Multiplexing

Certain events in the device may require host processor intervention and can be used to trigger interrupts to the host processor. Such event are an audio serial interface (ASI) bus error and input DC fault diagnostic faults. The device powers down the record channels if any faults are detected with the ASI bus error clocks, such as:

  • Invalid FSYNC frequency
  • Invalid SBCLK to FSYNC ratio
  • Long pauses of the SBCLK or FSYNC clocks

When an ASI bus clock error is detected, the device shuts down the record channel as quickly as possible. After all ASI bus clock errors are resolved, the device volume ramps back to its previous state to recover the record channel. During an ASI bus clock error, the internal interrupt request (IRQ) interrupt signal asserts low if the clock error interrupt mask register bit INT_MASK0[7], P0_R51_D7 is set low. The clock fault is also available for readback in the live fault status register bit INT_LIVE0, P1_R44 as well as latched to the fault status register bit INT_LTCH0, P0_R44, which is a read-only register. Reading the latched fault status register, INT_LTCH0, clears all latched fault statuses. The device can be additionally configured to route the internal IRQ interrupt signal on the GPIOx pins and also can be configured as an open-drain output so that these pins can be wire-ANDed to the open-drain interrupt outputs of other devices.

When an input DC fault event is detected, the internal IRQ signal is asserted if the interrupt mask registers INT_MASK1, P0_R42 and INT_MASK2, P0_R43 are configured appropriately to unmask all the desired fault diagnostics interrupts. Each input channel can be independently set for an interrupt mask. Table 44 and Table 45 list the mask settings available for the input DC diagnostics fault interrupts.

Table 44. Interrupt Mask Register-1 for DC Faults Diagnostic

P0_R42 : INT_MASK1 INTERRUPT MASK REGISTER 1 FOR DC FAULTS DIAGNOSTIC INTERRUPTS
INT_MASK1[7] Channel 1 input DC faults diagnostic interrupt mask and unmask register bit
INT_MASK1[6] Channel 2 input DC faults diagnostic interrupt mask and unmask register bit
INT_MASK1[5] Channel 3 input DC faults diagnostic interrupt mask and unmask register bit
INT_MASK1[4] Channel 4 input DC faults diagnostic interrupt mask and unmask register bit
INT_MASK1[3] Channel 5 input DC faults diagnostic interrupt mask and unmask register bit
INT_MASK1[2] Channel 6 input DC faults diagnostic interrupt mask and unmask register bit
INT_MASK1[1] Short to VBAT_IN (when VBAT_IN is lower than MICBIAS) fault interrupt mask and unmask register bit
INT_MASK1[0] Reserved

Table 45. Interrupt Mask Register-2 for DC Faults Diagnostic

P0_R43 : INT_MASK2 INTERRUPT MASK REGISTER 2 FOR DC FAULTS DIAGNOSTIC INTERRUPTS
INT_MASK2[7] Open input fault interrupt mask and unmask register bit for all channels
INT_MASK2[6] Inputs shorted each other fault interrupt mask and unmask register bit for all channels
INT_MASK2[5] INxP input shorted to ground fault interrupt mask and unmask register bit for all channels
INT_MASK2[4] INxM input shorted to ground fault interrupt mask and unmask register bit for all channels
INT_MASK2[3] INxP input shorted to MICBIAS fault interrupt mask and unmask register bit for all channels
INT_MASK2[2] INxM input shorted to MICBIAS fault interrupt mask and unmask register bit for all channels
INT_MASK2[1] INxP input shorted to VBAT_IN fault interrupt mask and unmask register bit for all channels
INT_MASK2[0] INxM input shorted to VBAT_IN fault interrupt mask and unmask register bit for all channels

The device supports the channel-specific input DC fault latched status registers for all channels from CH1_LTCH, P0_R46 to CH6_LTCH, P0_R51, which are read-only registers. The device also has a consolidated summary status register across channels for the input DC latched fault status register, CHx_LTCH, P0_R45 that the host can read to quickly know which channel fault has occurred. Reading the latched fault status registers, CH1_LTCH to CH6_LTCH, clears all the latched fault status including the summary status register, CHx_LTCH. Table 46 shows various input DC fault diagnostics status bits that are supported by the device.

Table 46. Input DC Faults Diagnostic Latched Status

P0_R46 : CH1_LTCH CHANNEL 1 INPUT FAULTS DIAGNOSTIC LATCHED STATUS
CH1_LTCH[7] Channel 1 open input fault detection status bit (self-clearing bit)
CH1_LTCH[6] Channel 1 inputs shorted together fault detection status bit (self-clearing bit)
CH1_LTCH[5] Channel 1 IN1P input shorted to ground fault detection status bit (self-clearing bit)
CH1_LTCH[4] Channel 1 IN1M input shorted to ground fault detection status bit (self-clearing bit)
CH1_LTCH[3] Channel 1 IN1P input shorted to MICBIAS fault detection status bit (self-clearing bit)
CH1_LTCH[2] Channel 1 IN1M input shorted to MICBIAS fault detection status bit (self-clearing bit)
CH1_LTCH[1] Channel 1 IN1P input shorted to VBAT_IN fault detection status bit (self-clearing bit)
CH1_LTCH[0] Channel 1 IN1M input shorted to VBAT_IN fault detection status bit (self-clearing bit)

Similarly, the DC faults diagnostic latched status for input channel 2 to channel 6 can be monitored using the CH2_LTCH (P0_R47) to CH6_LTCH (P0_R51) registers, respectively.

The device GPIOx pins can be additionally configured to route the internal IRQ interrupt signal on the GPIOx pins and also can be configured as an open-drain output so that this pin can be wire-ANDed to the open-drain interrupt outputs of other devices.

The IRQ interrupt signal can either be configured as an active low or active high polarity by setting the INT_POL, P0_R40_D7 register bit. This signal can also be configured as a single pulse or a series of pulses by programming the INT_EVENT[1:0], P0_R40_D[6:5] register bits. If the interrupts are configured as a series of pulses, the events trigger the start of pulses that stop when the latched fault status register is read to determine the cause of the interrupt.

The device also supports read-only live status registers that determine if all the channels are powered up or down and if the device is in sleep mode or not. These status registers are located in P0_R118, DEV_STS0 and P0_R119, DEV_STS1.

The device has a GPIO1 multifunction pin that can be configured for a desired specific function. Additionally the PCM6x40-Q1 has two more GPIO pins and two GPI pins supported that can be used in the system for various other features. Table 47 shows all possible allocation of these multifunction pins for all the various features.

Table 47. Multifunction Pin Assignments

ROW PIN FUNCTION GPIO1 GPIO2 GPIO3 GPI1 GPI2
— — GPIO1_CFG
[4:0] 		GPIO2_CFG
[4:0]		 GPIO3_CFG
[4:0]		 GPI1_CFG[4:0] GPI2_CFG[4:0]
— — P0_R33[7:4] P0_R34[7:4] P0_R35[7:4] P0_R36[7:4] P0_R37[7:4]
A Pin disabled S(1) S (default) S (default) S (default) S (default)
B General-purpose output (GPO) S S S NS(2) NS
C Interrupt output (IRQ) S (default) S S NS NS
D Secondary ASI output (SDOUT2) S S S NS NS
F MiCBIAS on/off input (BIASEN) S S S S S
G General-purpose input (GPI) S S S S S
H Master clock input (MCLK) S S S S S
I ASI daisy-chain input (SDIN) S S S S S
(1) S means the feature mentioned in this row is supported for the respective GPIO1, GPOx, or GPIx pin mentioned in this column.
(2) NS means the feature mentioned in this row is not supported for the respective GPIO1, GPOx, or GPIx pin mentioned in this column.

Each GPIOx pin can be independently set for the desired drive configurations setting using the GPIOx_DRV[3:0] register bits. Table 48 lists the drive configuration settings.

Table 48. GPIOx Pins Drive Configuration Settings

P0_R33_D[3:0] : GPIO1_DRV[3:0] GPIO OUTPUT DRIVE CONFIGURATION SETTINGS FOR GPIO1
000 The GPIO1 pin is set to high impedance (floated)
001 The GPIO1 pin is set to be driven active low or active high
010 (default) The GPIO1 pin is set to be driven active low or weak high (on-chip pullup)
011 The GPIO1 pin is set to be driven active low or Hi-Z (floated)
100 The GPIO1 pin is set to be driven weak low (on-chip pulldown) or active high
101 The GPIO1 pin is set to be driven Hi-Z (floated) or active high
110 and 111 Reserved (do not use these settings)

Similarly, the GPIO2 and GPIO3 pins can be configured using the GPIO2_DRV(P0_R34) and GPIO3_DRV(P0_R35) register bits, respectively.

When configured as a general-purpose output (GPO), the GPIOx pin values can be driven by writing the GPIO_VAL P0_R38 registers. The GPIO_MON, P0_R39 register can be used to readback the status of the GPIOx and GPIx pins when configured as a general-purpose input (GPI).