In addition to the gain calibration, the phase delay in each channel can be finely calibrated or adjusted in steps of one modulator clock cycle for a cycle range of 0 to 255 for the phase error. The modulator clock, the same clock used for ADC_MOD_CLK, is 6.144 MHz (the output data sample rate is multiples or submultiples of 48 kHz) or 5.6448 MHz (the output data sample rate is multiples or submultiples of 44.1 kHz). This feature is very useful for many applications that must match the phase with fine resolution between each channel, including any phase mismatch across channels resulting from external components or microphones. Table 13 shows the available programmable options for channel phase calibration.
|P0_R64_D[7:0] : CH1_PCAL[7:0]||CHANNEL PHASE CALIBRATION SETTING FOR INPUT CHANNEL 1|
|0000 0000 = 0d (default)||Input channel 1 phase calibration with no delay|
|0000 0001 = 1d||Input channel 1 phase calibration delay is set to one cycle of the modulator clock|
|0000 0010 = 2d||Input channel 1 phase calibration delay is set to two cycles of the modulator clock|
|1111 1110 = 254d||Input channel 1 phase calibration delay is set to 254 cycles of the modulator clock|
|1111 1111 = 255d||Input channel 1 phase calibration delay is set to 255 cycles of the modulator clock|
Similarly, the channel phase calibration setting for input channel 2 to channel 6 can be configured using the CH2_PCAL (P0_R69) to CH6_PCAL (P0_R89) register bits, respectively.