SBOS487B June 2009 – March 2020 PGA280
The six GPIO port pins can be configured individually in several modes: as inputs or outputs; a special CS mode; and a connection to the PGA280 internal special function register that contains control signals or indications. See Table 1 for details. The GPIO can be accessed through SPI as soon as supply voltage is connected to DVDD and DGND.
Input: Standard CMOS high-impedance input, no internal termination. Terminate externally if not used or set to output. Note: The GPIOs are all set as inputs after a device reset.
Output: Push-pull output. Output current is derived from DVDD and from DGND. Avoid I/O activity and high current during high-precision measurements to avoid coupled noise.
Special Function I/O: The configuration allows connecting a designated pin to the special function register (Register 12): OSCout, SYNCin, BUFAout, BUFTin, EFout, MUX2, MUX1, and MUX0. The pin must be configured as an input or output according to the pin function.
Example (CHKsum not enabled):
0x480B GPIO0, GPIO1. and GPIO3 set to output
0x4C0B GPIO0 and GPIO1 connected to MUX0 and MUX1, EFout connected to GPIO3. MUX0 and MUX1 are controlled from Register 0.