SBOS487B June 2009 – March 2020 PGA280
|MUX-D||IARerr||BUFA Pol||ICAerr||ED BUFA||OUTerr||GAINerr||IOVerr|
MUX-D: Set this bit to 1 to disable MUX control from Register 0; set to 0 after reset.
BUFA Pol: Controls BUF active indication polarity. Set to 0 for high = active; set to 1 for low = active.
ED BUFA Suppress: Error detection is normally disabled during BUFA active. Errors are not suppressed if ED BUFA = 1.
Error flags are logic OR-combined and connected to the EFout in Register 12 as well as connected to the GPIO3 output pin if configured. The EFout signal is active high. Assigned errors can be disabled individually using this OR function, with the exception of CHKerr, by writing a 1 to the error bit position. [IARerr; ICAerr; OUTerr; GAINerr; IOVerr]