SLDS204B October 2014 – June 2020 PGA300
PRODUCTION DATA.
The output of the digital compensation is clamped. The low and high clamp values are programmable using the LOW_CLAMP[15:0] and HIGH_CLAMP[15:0] bits in the EEPROM. In addition, a normal operating output can be configured using the NORMAL_LOW[15:0] and NORMAL_HIGH[15:0] bits in the EEPROM. Any output value from the digital compensation that exceeds the NORMAL_HIGH threshold gets driven to the HIGH_CLAMP value. Similarly, any output value below the NORMAL_LOW threshold gets driven to the LOW_CLAMP value. Figure 8 shows an example of the clamping feature for 0-V to 5-V voltage output mode. The output of the compensation can be configured in a similar way when the 4-mA to 20-mA current output mode is used. In such case, however, the LOW_CLAMP[15:0] value must be larger than the maximum supply current needed for normal operation of the device.