SLDS204B October   2014  – June 2020 PGA300

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      PGA300 Simplified Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Reverse Voltage Protection
    6. 6.6  Electrical Characteristics: Regulators
    7. 6.7  Electrical Characteristics: Internal References
    8. 6.8  Electrical Characteristics: Bridge Sensor Supply
    9. 6.9  Electrical Characteristics: External Temperature Sensor Supply
    10. 6.10 Electrical Characteristics: Internal Temperature Sensor
    11. 6.11 Electrical Characteristics: P Gain Stage (Chopper Stabilized)
    12. 6.12 Electrical Characteristics: P Analog-to-Digital Converter
    13. 6.13 Electrical Characteristics: T Gain Stage (Chopper Stabilized)
    14. 6.14 Electrical Characteristics: T Analog-to-Digital Converter
    15. 6.15 Electrical Characteristics: DAC Output
    16. 6.16 Electrical Characteristics: DAC Gain Stage
    17. 6.17 Electrical Characteristics: Diagnostics
    18. 6.18 Electrical Characteristics: One-Wire Interface
    19. 6.19 Electrical Characteristics: EEPROM (Non-Volatile Memory)
    20. 6.20 Electrical Characteristics: Power-Supply Currents
    21. 6.21 Electrical Characteristics: Timing
    22. 6.22 Electrical Characteristics: Accuracy
    23. 6.23 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Reverse-Voltage Protection Circuit
      2. 7.3.2  Linear Regulators
      3. 7.3.3  Internal References
        1. 7.3.3.1 High-Voltage Reference
        2. 7.3.3.2 Accurate Reference
      4. 7.3.4  Bridge Sensor Supply for Resistive Bridges (BRG+ to BRG–)
      5. 7.3.5  ITEMP Supply for External Temperature Sensors
      6. 7.3.6  Internal Temperature Sensor
      7. 7.3.7  Pressure Measurement Signal Chain
        1. 7.3.7.1 P Gain Stage
        2. 7.3.7.2 P Analog-to-Digital Converter
          1. 7.3.7.2.1 P Sigma-Delta Modulator for P ADC
          2. 7.3.7.2.2 P Decimation Filter for P ADC
      8. 7.3.8  Temperature Measurement Signal Chain
        1. 7.3.8.1 T Gain Stage
        2. 7.3.8.2 T Analog-to-Digital Converter
          1. 7.3.8.2.1 T Sigma-Delta Modulator for T ADC
          2. 7.3.8.2.2 T Decimation Filters for T ADC
      9. 7.3.9  DAC Output
        1. 7.3.9.1 Ratiometric vs Absolute Output Mode
      10. 7.3.10 DAC Gain Stage
      11. 7.3.11 Digital Compensation and Filter
        1. 7.3.11.1 Digital Gain and Offset Compensation
        2. 7.3.11.2 Temperature and Nonlinearity Compensation
          1. 7.3.11.2.1 Operating Without TC and NL Compensation
          2. 7.3.11.2.2 Temperature Compensation Using the Internal Temperature Sensor
        3. 7.3.11.3 Clamping
        4. 7.3.11.4 Digital IIR Filter
          1. 7.3.11.4.1 Filter Coefficients
            1. 7.3.11.4.1.1 No Filtering
            2. 7.3.11.4.1.2 Filter Coefficients for P ADC Sampling Rate = 128 µs
      12. 7.3.12 Diagnostics
        1. 7.3.12.1 Power-Supply Diagnostics
        2. 7.3.12.2 Signal Chain Diagnostics
          1. 7.3.12.2.1 P Gain and T Gain Input Diagnostics
          2. 7.3.12.2.2 P Gain and T Gain Output Diagnostics
          3. 7.3.12.2.3 Masking Signal Chain Diagnostics
        3. 7.3.12.3 Fault Detection Timing
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operating Modes
        1. 7.4.1.1 Execution Mode
        2. 7.4.1.2 Configuration Mode
      2. 7.4.2 Output Modes
        1. 7.4.2.1 Voltage Output Mode
        2. 7.4.2.2 Current Output Mode
    5. 7.5 Programming
      1. 7.5.1 One-Wire Interface (OWI)
        1. 7.5.1.1 Overview of OWI
        2. 7.5.1.2 Activating and Deactivating the OWI
          1. 7.5.1.2.1 Activating OWI Communication
          2. 7.5.1.2.2 Deactivating OWI Communication
        3. 7.5.1.3 OWI Protocol
          1. 7.5.1.3.1 OWI Frame Structure
            1. 7.5.1.3.1.1 Standard Field Structure
            2. 7.5.1.3.1.2 Frame Structure
            3. 7.5.1.3.1.3 Sync Field
            4. 7.5.1.3.1.4 Command Field
            5. 7.5.1.3.1.5 Data Fields
          2. 7.5.1.3.2 OWI Commands
            1. 7.5.1.3.2.1 OWI Write Command
            2. 7.5.1.3.2.2 OWI Read-Initialization Command
            3. 7.5.1.3.2.3 OWI Read-Response Command
            4. 7.5.1.3.2.4 OWI EEPROM Cache Burst-Write Command
            5. 7.5.1.3.2.5 OWI EEPROM Cache Burst-Read Command
          3. 7.5.1.3.3 OWI Operations
            1. 7.5.1.3.3.1 Write Operation
            2. 7.5.1.3.3.2 Read Operation
            3. 7.5.1.3.3.3 EEPROM Cache Burst Write
            4. 7.5.1.3.3.4 EEPROM Cache Burst Read
      2. 7.5.2 Memory
        1. 7.5.2.1 EEPROM Memory
          1. 7.5.2.1.1 EEPROM Cache
          2. 7.5.2.1.2 EEPROM Programming Procedure
          3. 7.5.2.1.3 EEPROM Programming Current
          4. 7.5.2.1.4 EEPROM Memory Map CRC
      3. 7.5.3 Control and Status Registers
    6. 7.6 Register Maps
      1. 7.6.1 Register Settings
      2. 7.6.2 Control and Status Registers
      3. 7.6.3 EEPROM Registers
      4. 7.6.4 Register Descriptions
        1. 7.6.4.1  MODE_CTRL Register (CS Register Page: 0x0) (CS Offset: 0x0C) (EEPROM Page: N/A) (EEPROM Offset: N/A)
          1. Table 14. MODE_CTRL Field Descriptions
        2. 7.6.4.2  PADC_DATA_LSB and PADC_DATA_MSB Registers (CS Register Page: 0x2) (CS Offset: 0x20, 0x21) (EEPROM Page: N/A) (EEPROM Offset: N/A)
        3. 7.6.4.3  TADC_DATA_LSB and TADC_DATA_MSB Registers (CS Register Page: 0x2) (CS Offset: 0x24, 0x25) (EEPROM Page: N/A) (EEPROM Offset: N/A)
        4. 7.6.4.4  DAC_REG_LSB and DAC_REG_MSB Registers (CS Register Page: 0x2) (CS Offset: 0x30, 0x31) (EEPROM Page: N/A) (EEPROM Offset: N/A)
        5. 7.6.4.5  TC and NL Compensation Coefficient (hx, gx, nx, and mx) Registers (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: see ) (EEPROM Offset: see )
        6. 7.6.4.6  Digital Filter Coefficient (ax and bx) Registers (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: see ) (EEPROM Offset: see )
        7. 7.6.4.7  NORMAL_LOW_LSB and NORMAL_LOW_MSB Registers (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0x5) (EEPROM Offset: 0x02, 0x03)
        8. 7.6.4.8  NORMAL_HIGH_LSB and NORMAL_HIGH_MSB Registers (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0x5) (EEPROM Offset: 0x04, 0x05)
        9. 7.6.4.9  LOW_CLAMP_LSB and LOW_CLAMP_MSB Registers (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0x5) (EEPROM Offset: 0x06, 0x07)
        10. 7.6.4.10 HIGH_CLAMP_LSB and HIGH_CLAMP_MSB Registers (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0x6) (EEPROM Offset: 0x00, 0x01)
        11. 7.6.4.11 PADC_GAIN_LSB and PADC_GAIN_MSB Registers (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0x6) (EEPROM Offset: 0x02, 0x03)
        12. 7.6.4.12 PADC_OFFSET_LSB and PADC_OFFSET_MSB Registers (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0x6) (EEPROM Offset: 0x04, 0x05)
        13. 7.6.4.13 DAC_FAULT_LSB and DAC_FAULT_MSB Registers (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0x9) (EEPROM Offset: 0x02, 0x03)
        14. 7.6.4.14 TADC_GAIN_LSB and TADC_GAIN_MSB Registers (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0x9) (EEPROM Offset: 0x04, 0x05)
        15. 7.6.4.15 TADC_OFFSET_LSB and TADC_OFFSET_MSB Registers (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0x9) (EEPROM Offset: 0x06, 0x07)
        16. 7.6.4.16 SERIAL_NUMBER_BYTE0/1/2/3 Registers (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0xA) (EEPROM Offset: 0x00, 0x01, 0x02, 0x03)
        17. 7.6.4.17 DAC_CONFIG Register (CS Register Page: 0x2) (CS Offset: 0x39) (EEPROM Page: 0x4) (EEPROM Offset: 0x00)
          1. Table 15. DAC_CONFIG Register Field Descriptions
        18. 7.6.4.18 OP_STAGE_CTRL Register (CS Register Page: 0x2) (CS Offset: 0x3B) (EEPROM Page: 0x4) (EEPROM Offset: 0x01)
          1. Table 16. OP_STAGE_CTRL Register Field Descriptions
        19. 7.6.4.19 TEST_CTRL Register (CS Register Page: 0x02) (CS Offset: 0x67) (EEPROM Page: N/A) (EEPROM Offset: N/A)
          1. Table 17. TEST_CTRL Register Field Descriptions
        20. 7.6.4.20 BRDG_CTRL Register (CS Register Page: 0x2) (CS Offset: 0x46) (EEPROM Page: 0x4) (EEPROM Offset: 0x02)
          1. Table 18. BRDG_CTRL Register Field Descriptions
        21. 7.6.4.21 P_GAIN_SELECT Register (CS Register Page: 0x2) (CS Offset: 0x47) (EEPROM Page: 0x4) (EEPROM Offset: 0x03)
          1. Table 19. P_GAIN_SELECT Register Field Descriptions
        22. 7.6.4.22 T_GAIN_SELECT Register (CS Register Page: 0x2) (CS Offset: 0x48) (EEPROM Page: 0x4) (EEPROM Offset: 0x04)
          1. Table 20. T_GAIN_SELECT Register Field Descriptions
        23. 7.6.4.23 TEMP_CTRL Register (CS Register Page: 0x2) (CS Offset: 0x4C) (EEPROM Page: 0x4) (EEPROM Offset: 0x05)
          1. Table 21. TEMP_CTRL Register Field Descriptions
        24. 7.6.4.24 TEMP_SE Register (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0x5) (EEPROM Offset: 0x00)
          1. Table 22. TEMP_SE Register Field Descriptions
        25. 7.6.4.25 DIAG_ENABLE Register (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0x8) (EEPROM Offset: 0x04)
          1. Table 23. DIAG_ENABLE Register Field Descriptions
        26. 7.6.4.26 AFEDIAG_MASK Register (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0x8) (EEPROM Offset: 0x07)
          1. Table 24. AFEDIAG_MASK Register Field Descriptions
        27. 7.6.4.27 AFEDIAG_CFG Register (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0x8) (EEPROM Offset: 0x06)
          1. Table 25. AFEDIAG_CFG Register Field Descriptions
        28. 7.6.4.28 AFEDIAG (CS Register Page: 0x2) (CS Offset: 0x5A) (EEPROM Page: N/A) (EEPROM Offset: N/A)
          1. Table 26. AFEDIAG Register Field Descriptions
        29. 7.6.4.29 EEPROM_LOCK Register (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0x8) (EEPROM Offset: 0x05)
          1. Table 27. EEPROM_LOCK Field Descriptions
        30. 7.6.4.30 EEPROM_PAGE_ADDRESS Register (CS Register Page: 0x5) (CS Offset: 0x88) (EEPROM Page: N/A) (EEPROM Offset: N/A)
          1. Table 28. EEPROM_PAGE_ADDRESS Field Descriptions
        31. 7.6.4.31 EEPROM_CTRL Register (CS Register Page: 0x5) (CS Offset: 0x89) (EEPROM Page: N/A) (EEPROM Offset: N/A)
          1. Table 29. EEPROM_CTRL Field Descriptions
        32. 7.6.4.32 EEPROM_STATUS Register (CS Register Page: 0x5) (CS Offset: 0x8B) (EEPROM Page: N/A) (EEPROM Offset: N/A)
          1. Table 30. EEPROM_STATUS Field Descriptions
        33. 7.6.4.33 EEPROM_CRC Register (CS Register Page: 0x5) (CS Offset: 0x8A) (EEPROM Page: N/A) (EEPROM Offset: N/A)
          1. Table 31. EEPROM_CRC Field Descriptions
        34. 7.6.4.34 EEPROM_CRC_STATUS Register (CS Register Page: 0x5) (CS Offset: 0x8C) (EEPROM Page: N/A) (EEPROM Offset: N/A)
          1. Table 32. EEPROM_CRC_STATUS Field Descriptions
        35. 7.6.4.35 EEPROM_CRC_VALUE_CALC Register (CS Register Page: 0x5) (CS Offset: 0x8D) (EEPROM Page: N/A) (EEPROM Offset: N/A)
          1. Table 33. EEPROM_CRC_VALUE_CALC Field Descriptions
        36. 7.6.4.36 EEPROM_CRC_VALUE_USER Register (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0xF) (EEPROM Offset: 0x07)
          1. Table 34. EEPROM_CRC_VALUE_USER Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Harness Open-Wire Diagnostics
    2. 8.2 Typical Applications
      1. 8.2.1 4-mA to 20-mA Current Output
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 External Components
          2. 8.2.1.2.2 Programming and EEPROM Settings
        3. 8.2.1.3 Application Curve
      2. 8.2.2 0-V to 10-V Absolute Voltage Output
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 External Components
            1. 8.2.2.2.1.1 Programming and EEPROM Settings
      3. 8.2.3 0-V to 5-V Ratiometric Voltage Output
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
          1. 8.2.3.2.1 External Components
          2. 8.2.3.2.2 Programming and EEPROM Settings
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6.3 EEPROM Registers

Table 12. EEPROM Register Map

Register Name Offset R/W D7 D6 D5 D4 D3 D2 D1 D0
EEPROM Page 0 (ADDR[3:0] = 0x0)
H0_LSB 0x00 R/W H0[7:0]
H0_MSB 0x01 R/W H0[15:8]
G0_LSB 0x02 R/W G0[7:0]
G0_MSB 0x03 R/W G0[15:8]
N0_LSB 0x04 R/W N0[7:0]
N0_MSB 0x05 R/W N0[15:8]
H1_LSB 0x06 R/W H1[7:0]
H1_MSB 0x07 R/W H1[15:8]
EEPROM Page 1 (ADDR[3:0] = 0x1)
G1_LSB 0x00 R/W G1[7:0]
G1_MSB 0x01 R/W G1[15:8]
N1_LSB 0x02 R/W N1[7:0]
N1_MSB 0x03 R/W N1[15:8]
H2_LSB 0x04 R/W H2[7:0]
H2_MSB 0x05 R/W H2[15:8]
G2_LSB 0x06 R/W G2[7:0]
G2_MSB 0x07 R/W G2[15:8]
EEPROM Page 2 (ADDR[3:0] = 0x2)
N2_LSB 0x00 R/W N2[7:0]
N2_MSB 0x01 R/W N2[15:8]
A0_LSB 0x02 R/W A0[7:0]
A0_MSB 0x03 R/W A0[15:8]
A1_LSB 0x04 R/W A1[7:0]
A1_MSB 0x05 R/W A1[15:8]
A2_LSB 0x06 R/W A2[7:0]
A2_MSB 0x07 R/W A2[15:8]
EEPROM Page 3 (ADDR[3:0] = 0x3)
B0_LSB 0x00 R/W B0[7:0]
B0_MSB 0x01 R/W B0[15:8]
B1_LSB 0x02 R/W B1[7:0]
B1_MSB 0x03 R/W B1[15:8]
B2_LSB 0x04 R/W B2[7:0]
B2_MSB 0x05 R/W B2[15:8]
RESERVED 0x06 R/W RESERVED
RESERVED 0x07 R/W RESERVED
EEPROM Page 4 (ADDR[3:0] = 0x4)
DAC_CONFIG(1) 0x00 R/W RESERVED DAC_
RATIOMETRIC
OP_STAGE_CTRL(1) 0x01 R/W RESERVED DACCAP_EN 4_20MA_EN DAC_GAIN[2:0]
BRDG_CTRL(1) 0x02 R/W RESERVED VBRDG_ CTRL[1:0] RESERVED
P_GAIN_ SELECT(1) 0x03 R/W P_INV RESERVED P_GAIN[4:0]
T_GAIN_ SELECT(1) 0x04 R/W T_INV RESERVED T_GAIN[1:0]
TEMP_CTRL(1) 0x05 R/W RESERVED ITEMP_ CTRL[2:0] TEMP_MUX_ CTRL[3:0]
RESERVED 0x06 R/W RESERVED
RESERVED 0x07 R/W RESERVED
EEPROM Page 5 (ADDR[3:0] = 0x5)
TEMP_SE 0x00 R/W RESERVED TEMP_SE
RESERVED 0x01 R/W RESERVED
NORMAL_LOW_LSB 0x02 R/W NORMAL_LOW[7:0]
NORMAL_LOW_MSB 0x03 R/W RESERVED NORMAL_LOW[13:8]
NORMAL_HIGH_LSB 0x04 R/W NORMAL_HIGH[7:0]
NORMAL_HIGH_MSB 0x05 R/W RESERVED NORMAL_HIGH[13:8]
LOW_CLAMP_LSB 0x06 R/W LOW_CLAMP[7:0]
LOW_CLAMP_MSB 0x07 R/W RESERVED LOW_CLAMP[13:8]
EEPROM Page 6 (ADDR[3:0] = 0x6)
HIGH_CLAMP_LSB 0x00 R/W HIGH_CLAMP[7:0]
HIGH_CLAMP_MSB 0x01 R/W RESERVED HIGH_CLAMP[13:8]
PADC_GAIN_LSB 0x02 R/W PADC_GAIN[7:0]
PADC_GAIN_MSB 0x03 R/W PADC_GAIN[15:8]
PADC_OFFSET_LSB 0x04 R/W PADC_OFFSET[7:0]
PADC_OFFSET_MSB 0x05 R/W PADC_OFFSET[15:8]
H3_LSB 0x06 R/W H3[7:0]
H3_MSB 0x07 R/W H3[15:8]
EEPROM Page 7 (ADDR[3:0] = 0x7)
G3_LSB 0x00 R/W G3[7:0]
G3_MSB 0x01 R/W G3[15:8]
N3_LSB 0x02 R/W N3[7:0]
N3_MSB 0x03 R/W N3[15:8]
M0_LSB 0x04 R/W M0[7:0]
M0_MSB 0x05 R/W M0[15:8]
M1_MSB 0x06 R/W M1[7:0]
M1_LSB 0x07 R/W M1[15:8]
EEPROM Page 8 (ADDR[3:0] = 0x8)
M2_LSB 0x00 R/W M2[7:0]
M2_MSB 0x01 R/W M2[15:8]
M3_LSB 0x02 R/W M3[7:0]
M3_MSB 0x03 R/W M3[15:8]
DIAG_ENABLE 0x04 R/W RESERVED DIAG_
ENABLE
EEPROM_LOCK 0x05 R/W RESERVED EEPROM_
LOCK
AFEDIAG_CFG 0x06 R/W RESERVED DIS_R_T DIS_R_P THRS[2:0] PD[1:0]
AFEDIAG_MASK 0x07 R/W TGAIN_UV TGAIN_OV PGAIN_UV PGAIN_OV RESERVED INT_OV INP_UV INP_OV
EEPROM Page 9 (ADDR[3:0] = 0x9)
RESERVED 0x00 R/W RESERVED
RESERVED 0x01 R/W RESERVED
DAC_FAULT_LSB 0x02 R/W DAC_FAULT[7:0]
DAC_FAULT_MSB 0x03 R/W RESERVED DAC_FAULT[13:8]
TADC_GAIN_LSB 0x04 R/W TADC_GAIN[7:0]
TADC_GAIN_MSB 0x05 R/W TADC_GAIN[15:8]
TADC_OFFSET_LSB 0x06 R/W TADC_OFFSET[7:0]
TADC_OFFSET_MSB 0x07 R/W TADC_OFFSET[15:8]
EEPROM Page 10 (ADDR[3:0] = 0xA)
SERIAL_NUMBER_BYTE0 0x00 R/W SERIAL_NUMBER_BYTE0[7:0]
SERIAL_NUMBER_BYTE1 0x01 R/W SERIAL_NUMBER_BYTE1[7:0]
SERIAL_NUMBER_BYTE2 0x02 R/W SERIAL_NUMBER_BYTE2[7:0]
SERIAL_NUMBER_BYTE3 0x03 R/W SERIAL_NUMBER_BYTE3[7:0]
RESERVED 0x04 R/W RESERVED
RESERVED 0x05 R/W RESERVED
RESERVED 0x06 R/W RESERVED
RESERVED 0x07 R/W RESERVED
EEPROM Page 15 (ADDR[3:0] = 0xF)
RESERVED 0x00 R/W RESERVED
RESERVED 0x01 R/W RESERVED
RESERVED 0x02 R/W RESERVED
RESERVED 0x03 R/W RESERVED
RESERVED 0x04 R/W RESERVED
RESERVED 0x05 R/W RESERVED
RESERVED 0x06 R/W RESERVED
EEPROM_CRC_VALUE_
USER		 0x07 R/W EEPROM_ CRC_USER[7:0]
(1) Register exists both in the control and status register map and the EEPROM register map. The settings of the EEPROM registers take effect when in execution mode.

Table 13 shows the factory programmed default values of the EEPROM. Do not change byte values marked in red font from their respective default values, otherwise the device does not operate as specified. Always write the default values as shown in Table 13 to the red marked bytes.

Table 13. EEPROM Default Values

EEPROM Page BYTE 0 BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 BYTE 7
0x0 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x1 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x2 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x3 0x00 0x00 0x00 0x00 0x00 0x00 0xFF 0xFF
0x4 0x00 0x08 0x00 0x00 0x00 0x40 0xFF 0x01
0x5 0x00 0xFF 0x67 0x06 0x9A 0x39 0x34 0x03
0x6 0xCF 0x3C 0x01 0x00 0x00 0x00 0x00 0x00
0x7 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x8 0x00 0x00 0x00 0x00 0x00 0x00 0x07 0x33
0x9 0xFF 0xFF 0xDD 0xCC 0x01 0x00 0x00 0x00
0xA 0x00 0x00 0x00 0x00 0xFF 0xFF 0xFF 0xFF
0xB 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF
0xC 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF
0xD 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF
0xE 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF
0xF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xB8