SLASEC8B February   2017  – January 2019 PGA460-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Typical Application Diagram (Transformer Drive)
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Internal Supply Regulators Characteristics
    6. 6.6  Transducer Driver Characteristics
    7. 6.7  Transducer Receiver Characteristics
    8. 6.8  Analog to Digital Converter Characteristics
    9. 6.9  Digital Signal Processing Characteristics
    10. 6.10 Temperature Sensor Characteristics
    11. 6.11 High-Voltage I/O Characteristics
    12. 6.12 Digital I/O Characteristics
    13. 6.13 EEPROM Characteristics
    14. 6.14 Timing Requirements
    15. 6.15 Switching Characteristics
    16. 6.16 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power-Supply Block
      2. 7.3.2  Burst Generation
        1. 7.3.2.1 Using Center-Tap Transformer
        2. 7.3.2.2 Direct Drive
        3. 7.3.2.3 Other Configurations
      3. 7.3.3  Analog Front-End
      4. 7.3.4  Digital Signal Processing
        1. 7.3.4.1 Ultrasonic Echo—Band-Pass Filter
        2. 7.3.4.2 Ultrasonic Echo–Rectifier, Peak Hold, Low-Pass Filter, and Data Selection
        3. 7.3.4.3 Ultrasonic Echo—Nonlinear Scaling
        4. 7.3.4.4 Ultrasonic Echo—Threshold Data Assignment
        5. 7.3.4.5 Digital Gain
      5. 7.3.5  System Diagnostics
        1. 7.3.5.1 Device Internal Diagnostics
      6. 7.3.6  Interface Description
        1. 7.3.6.1 Time-Command Interface
          1. 7.3.6.1.1 RUN Commands
          2. 7.3.6.1.2 CONFIGURATION/STATUS Command
        2. 7.3.6.2 USART Interface
          1. 7.3.6.2.1 USART Asynchronous Mode
            1. 7.3.6.2.1.1 Sync Field
            2. 7.3.6.2.1.2 Command Field
            3. 7.3.6.2.1.3 Data Fields
            4. 7.3.6.2.1.4 Checksum Field
            5. 7.3.6.2.1.5 PGA460-Q1 UART Commands
            6. 7.3.6.2.1.6 UART Operations
              1. 7.3.6.2.1.6.1 No-Response Operation
              2. 7.3.6.2.1.6.2 Response Operation (All Except Register Read)
              3. 7.3.6.2.1.6.3 Response Operation (Register Read)
            7. 7.3.6.2.1.7 Diagnostic Field
            8. 7.3.6.2.1.8 USART Synchronous Mode
          2. 7.3.6.2.2 One-Wire UART Interface
          3. 7.3.6.2.3 Ultrasonic Object Detection Through UART Operations
        3. 7.3.6.3 In-System IO-Pin Interface Selection
      7. 7.3.7  Echo Data Dump
        1. 7.3.7.1 On-Board Memory Data Store
        2. 7.3.7.2 Direct Data Burst Through USART Synchronous Mode
      8. 7.3.8  Low-Power Mode
        1. 7.3.8.1 Time-Command Interface
        2. 7.3.8.2 UART Interface
      9. 7.3.9  Transducer Time and Temperature Decoupling
        1. 7.3.9.1 Time Decoupling
        2. 7.3.9.2 Temperature Decoupling
      10. 7.3.10 Memory CRC Calculation
      11. 7.3.11 Temperature Sensor and Temperature Data-Path
      12. 7.3.12 TEST Pin Functionality
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 UART and USART Communication Examples
    6. 7.6 Register Maps
      1. 7.6.1 EEPROM Programming
      2. 7.6.2 Register Map Partitioning and Default Values
      3. 7.6.3 REGMAP Registers
        1. 7.6.3.1  USER_DATA1 Register (Address = 0h) [reset = 0h]
          1. Table 9. USER_DATA1 Register Field Descriptions
        2. 7.6.3.2  USER_DATA2 Register (Address = 1h) [reset = 0h]
          1. Table 10. USER_DATA2 Register Field Descriptions
        3. 7.6.3.3  USER_DATA3 Register (Address = 2h) [reset = 0h]
          1. Table 11. USER_DATA3 Register Field Descriptions
        4. 7.6.3.4  USER_DATA4 Register (Address = 3h) [reset = 0h]
          1. Table 12. USER_DATA4 Register Field Descriptions
        5. 7.6.3.5  USER_DATA5 Register (Address = 4h) [reset = 0h]
          1. Table 13. USER_DATA5 Register Field Descriptions
        6. 7.6.3.6  USER_DATA6 Register (Address = 5h) [reset = 0h]
          1. Table 14. USER_DATA6 Register Field Descriptions
        7. 7.6.3.7  USER_DATA7 Register (Address = 6h) [reset = 0h]
          1. Table 15. USER_DATA7 Register Field Descriptions
        8. 7.6.3.8  USER_DATA8 Register (Address = 7h) [reset = 0h]
          1. Table 16. USER_DATA8 Register Field Descriptions
        9. 7.6.3.9  USER_DATA9 Register (Address = 8h) [reset = 0h]
          1. Table 17. USER_DATA9 Register Field Descriptions
        10. 7.6.3.10 USER_DATA10 Register (Address = 9h) [reset = 0h]
          1. Table 18. USER_DATA10 Register Field Descriptions
        11. 7.6.3.11 USER_DATA11 Register (Address = Ah) [reset = 0h]
          1. Table 19. USER_DATA11 Register Field Descriptions
        12. 7.6.3.12 USER_DATA12 Register (Address = Bh) [reset = 0h]
          1. Table 20. USER_DATA12 Register Field Descriptions
        13. 7.6.3.13 USER_DATA13 Register (Address = Ch) [reset = 0h]
          1. Table 21. USER_DATA13 Register Field Descriptions
        14. 7.6.3.14 USER_DATA14 Register (Address = Dh) [reset = 0h]
          1. Table 22. USER_DATA14 Register Field Descriptions
        15. 7.6.3.15 USER_DATA15 Register (Address = Eh) [reset = 0h]
          1. Table 23. USER_DATA15 Register Field Descriptions
        16. 7.6.3.16 USER_DATA16 Register (Address = Fh) [reset = 0h]
          1. Table 24. USER_DATA16 Register Field Descriptions
        17. 7.6.3.17 USER_DATA17 Register (Address = 10h) [reset = 0h]
          1. Table 25. USER_DATA17 Register Field Descriptions
        18. 7.6.3.18 USER_DATA18 Register (Address = 11h) [reset = 0h]
          1. Table 26. USER_DATA18 Register Field Descriptions
        19. 7.6.3.19 USER_DATA19 Register (Address = 12h) [reset = 0h]
          1. Table 27. USER_DATA19 Register Field Descriptions
        20. 7.6.3.20 USER_DATA20 Register (Address = 13h) [reset = 0h]
          1. Table 28. USER_DATA20 Register Field Descriptions
        21. 7.6.3.21 TVGAIN0 Register (Address = 14h) [reset = 0h]
          1. Table 29. TVGAIN0 Register Field Descriptions
        22. 7.6.3.22 TVGAIN1 Register (Address = 15h) [reset = 0h]
          1. Table 30. TVGAIN1 Register Field Descriptions
        23. 7.6.3.23 TVGAIN2 Register (Address = 16h) [reset = 0h]
          1. Table 31. TVGAIN2 Register Field Descriptions
        24. 7.6.3.24 TVGAIN3 Register (Address = 17h) [reset = 0h]
          1. Table 32. TVGAIN3 Register Field Descriptions
        25. 7.6.3.25 TVGAIN4 Register (Address = 18h) [reset = 0h]
          1. Table 33. TVGAIN4 Register Field Descriptions
        26. 7.6.3.26 TVGAIN5 Register (Address = 19h) [reset = 0h]
          1. Table 34. TVGAIN5 Register Field Descriptions
        27. 7.6.3.27 TVGAIN6 Register (Address = 1Ah) [reset = 0h]
          1. Table 35. TVGAIN6 Register Field Descriptions
        28. 7.6.3.28 INIT_GAIN Register (Address = 1Bh) [reset = 0h]
          1. Table 36. INIT_GAIN Register Field Descriptions
        29. 7.6.3.29 FREQUENCY Register (Address = 1Ch) [reset = 0h]
          1. Table 37. FREQUENCY Register Field Descriptions
        30. 7.6.3.30 DEADTIME Register (Address = 1Dh) [reset = 0h]
          1. Table 38. DEADTIME Register Field Descriptions
        31. 7.6.3.31 PULSE_P1 Register (Address = 1Eh) [reset = 0h]
          1. Table 39. PULSE_P1 Register Field Descriptions
        32. 7.6.3.32 PULSE_P2 Register (Address = 1Fh) [reset = 0h]
          1. Table 40. PULSE_P2 Register Field Descriptions
        33. 7.6.3.33 CURR_LIM_P1 Register (Address = 20h) [reset = 0h]
          1. Table 41. CURR_LIM_P1 Register Field Descriptions
        34. 7.6.3.34 CURR_LIM_P2 Register (Address = 21h) [reset = 0h]
          1. Table 42. CURR_LIM_P2 Register Field Descriptions
        35. 7.6.3.35 REC_LENGTH Register (Address = 22h) [reset = 0h]
          1. Table 43. REC_LENGTH Register Field Descriptions
        36. 7.6.3.36 FREQ_DIAG Register (Address = 23h) [reset = 0h]
          1. Table 44. FREQ_DIAG Register Field Descriptions
        37. 7.6.3.37 SAT_FDIAG_TH Register (Address = 24h) [reset = 0h]
          1. Table 45. SAT_FDIAG_TH Register Field Descriptions
        38. 7.6.3.38 FVOLT_DEC Register (Address = 25h) [reset = 0h]
          1. Table 46. FVOLT_DEC Register Field Descriptions
        39. 7.6.3.39 DECPL_TEMP Register (Address = 26h) [reset = 0h]
          1. Table 47. DECPL_TEMP Register Field Descriptions
        40. 7.6.3.40 DSP_SCALE Register (Address = 27h) [reset = 0h]
          1. Table 48. DSP_SCALE Register Field Descriptions
        41. 7.6.3.41 TEMP_TRIM Register (Address = 28h) [reset = 0h]
          1. Table 49. TEMP_TRIM Register Field Descriptions
        42. 7.6.3.42 P1_GAIN_CTRL Register (Address = 29h) [reset = 0h]
          1. Table 50. P1_GAIN_CTRL Register Field Descriptions
        43. 7.6.3.43 P2_GAIN_CTRL Register (Address = 2Ah) [reset = 0h]
          1. Table 51. P2_GAIN_CTRL Register Field Descriptions
        44. 7.6.3.44 EE_CRC Register (Address = 2Bh) [reset = 0h]
          1. Table 52. EE_CRC Register Field Descriptions
        45. 7.6.3.45 EE_CNTRL Register (Address = 40h) [reset = 00h]
          1. Table 53. EE_CNTRL Register Field Descriptions
        46. 7.6.3.46 BPF_A2_MSB Register (Address = 41h) [reset = 00h]
          1. Table 54. BPF_A2_MSB Register Field Descriptions
        47. 7.6.3.47 BPF_A2_LSB Register (Address = 42h) [reset = 00h]
          1. Table 55. BPF_A2_LSB Register Field Descriptions
        48. 7.6.3.48 BPF_A3_MSB Register (Address = 43h) [reset = 00h]
          1. Table 56. BPF_A3_MSB Register Field Descriptions
        49. 7.6.3.49 BPF_A3_LSB Register (Address = 44h) [reset = 00h]
          1. Table 57. BPF_A3_LSB Register Field Descriptions
        50. 7.6.3.50 BPF_B1_MSB Register (Address = 45h) [reset = 00h]
          1. Table 58. BPF_B1_MSB Register Field Descriptions
        51. 7.6.3.51 BPF_B1_LSB Register (Address = 46h) [reset = 00h]
          1. Table 59. BPF_B1_LSB Register Field Descriptions
        52. 7.6.3.52 LPF_A2_MSB Register (Address = 47h) [reset = 00h]
          1. Table 60. LPF_A2_MSB Register Field Descriptions
        53. 7.6.3.53 LPF_A2_LSB Register (Address = 48h) [reset = 00h]
          1. Table 61. LPF_A2_LSB Register Field Descriptions
        54. 7.6.3.54 LPF_B1_MSB Register (Address = 49h) [reset = 00h]
          1. Table 62. LPF_B1_MSB Register Field Descriptions
        55. 7.6.3.55 LPF_B1_LSB Register (Address = 4Ah) [reset = 00h]
          1. Table 63. LPF_B1_LSB Register Field Descriptions
        56. 7.6.3.56 TEST_MUX Register (Address = 4Bh) [reset = 00h]
          1. Table 64. TEST_MUX Register Field Descriptions
        57. 7.6.3.57 DEV_STAT0 Register (Address = 4Ch) [reset = 84h]
          1. Table 65. DEV_STAT0 Register Field Descriptions
        58. 7.6.3.58 DEV_STAT1 Register (Address = 4Dh) [reset = 00h]
          1. Table 66. DEV_STAT1 Register Field Descriptions
        59. 7.6.3.59 P1_THR_0 Register (Address = 5Fh) [reset = X]
          1. Table 67. P1_THR_0 Register Field Descriptions
        60. 7.6.3.60 P1_THR_1 Register (Address = 60h) [reset = X]
          1. Table 68. P1_THR_1 Register Field Descriptions
        61. 7.6.3.61 P1_THR_2 Register (Address = 61h) [reset = X]
          1. Table 69. P1_THR_2 Register Field Descriptions
        62. 7.6.3.62 P1_THR_3 Register (Address = 62h) [reset = X]
          1. Table 70. P1_THR_3 Register Field Descriptions
        63. 7.6.3.63 P1_THR_4 Register (Address = 63h) [reset = X]
          1. Table 71. P1_THR_4 Register Field Descriptions
        64. 7.6.3.64 P1_THR_5 Register (Address = 64h) [reset = X]
          1. Table 72. P1_THR_5 Register Field Descriptions
        65. 7.6.3.65 P1_THR_6 Register (Address = 65h) [reset = X]
          1. Table 73. P1_THR_6 Register Field Descriptions
        66. 7.6.3.66 P1_THR_7 Register (Address = 66h) [reset = X]
          1. Table 74. P1_THR_7 Register Field Descriptions
        67. 7.6.3.67 P1_THR_8 Register (Address = 67h) [reset = X]
          1. Table 75. P1_THR_8 Register Field Descriptions
        68. 7.6.3.68 P1_THR_9 Register (Address = 68h) [reset = X]
          1. Table 76. P1_THR_9 Register Field Descriptions
        69. 7.6.3.69 P1_THR_10 Register (Address = 69h) [reset = X]
          1. Table 77. P1_THR_10 Register Field Descriptions
        70. 7.6.3.70 P1_THR_11 Register (Address = 6Ah) [reset = X]
          1. Table 78. P1_THR_11 Register Field Descriptions
        71. 7.6.3.71 P1_THR_12 Register (Address = 6Bh) [reset = X]
          1. Table 79. P1_THR_12 Register Field Descriptions
        72. 7.6.3.72 P1_THR_13 Register (Address = 6Ch) [reset = X]
          1. Table 80. P1_THR_13 Register Field Descriptions
        73. 7.6.3.73 P1_THR_14 Register (Address = 6Dh) [reset = X]
          1. Table 81. P1_THR_14 Register Field Descriptions
        74. 7.6.3.74 P1_THR_15 Register (Address = 6Eh) [reset = X]
          1. Table 82. P1_THR_15 Register Field Descriptions
        75. 7.6.3.75 P2_THR_0 Register (Address = 6Fh) [reset = X]
          1. Table 83. P2_THR_0 Register Field Descriptions
        76. 7.6.3.76 P2_THR_1 Register (Address = 70h) [reset = X]
          1. Table 84. P2_THR_1 Register Field Descriptions
        77. 7.6.3.77 P2_THR_2 Register (Address = 71h) [reset = X]
          1. Table 85. P2_THR_2 Register Field Descriptions
        78. 7.6.3.78 P2_THR_3 Register (Address = 72h) [reset = X]
          1. Table 86. P2_THR_3 Register Field Descriptions
        79. 7.6.3.79 P2_THR_4 Register (Address = 73h) [reset = X]
          1. Table 87. P2_THR_4 Register Field Descriptions
        80. 7.6.3.80 P2_THR_5 Register (Address = 74h) [reset = X]
          1. Table 88. P2_THR_5 Register Field Descriptions
        81. 7.6.3.81 P2_THR_6 Register (Address = 75h) [reset = X]
          1. Table 89. P2_THR_6 Register Field Descriptions
        82. 7.6.3.82 P2_THR_7 Register (Address = 76h) [reset = X]
          1. Table 90. P2_THR_7 Register Field Descriptions
        83. 7.6.3.83 P2_THR_8 Register (Address = 77h) [reset = X]
          1. Table 91. P2_THR_8 Register Field Descriptions
        84. 7.6.3.84 P2_THR_9 Register (Address = 78h) [reset = X]
          1. Table 92. P2_THR_9 Register Field Descriptions
        85. 7.6.3.85 P2_THR_10 Register (Address = 79h) [reset = X]
          1. Table 93. P2_THR_10 Register Field Descriptions
        86. 7.6.3.86 P2_THR_11 Register (Address = 7Ah) [reset = X]
          1. Table 94. P2_THR_11 Register Field Descriptions
        87. 7.6.3.87 P2_THR_12 Register (Address = 7Bh) [reset = X]
          1. Table 95. P2_THR_12 Register Field Descriptions
        88. 7.6.3.88 P2_THR_13 Register (Address = 7Ch) [reset = X]
          1. Table 96. P2_THR_13 Register Field Descriptions
        89. 7.6.3.89 P2_THR_14 Register (Address = 7Dh) [reset = X]
          1. Table 97. P2_THR_14 Register Field Descriptions
        90. 7.6.3.90 P2_THR_15 Register (Address = 7Eh) [reset = X]
          1. Table 98. P2_THR_15 Register Field Descriptions
        91. 7.6.3.91 THR_CRC Register (Address = 7Fh) [reset = X]
          1. Table 99. THR_CRC Register Field Descriptions
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Transducer Types
    2. 8.2 Typical Applications
      1. 8.2.1 Transformer-Driven Method
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Transducer Driving Voltage
          2. 8.2.1.2.2 Transducer Driving Frequency
          3. 8.2.1.2.3 Transducer Pulse Count
          4. 8.2.1.2.4 Transformer Turns Ratio
          5. 8.2.1.2.5 Transformer Saturation Current and Main Voltage Rating
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Direct-Driven (Transformer-Less) Method
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

CONFIGURATION/STATUS Command

The CONFIGURATION/STATUS command is used for the following:

  • PGA460-Q1 internal parameter configuration
  • Time-varying gain and threshold setup
  • EEPROM programing
  • Diagnostics and temperature measurements
  • Echo data-dump function

When the CONFIGURATION/STATUS command is issued, the remaining data is transferred by using bit-like communication where a logical 1 and logical 0 are encoded as shown in Figure 13. Figure 17 and Figure 18 show a full-length CONFIGURATION/STATUS command.

PGA460-Q1 td_tc_config_stat_wrt_slasec8.gifFigure 17. Time-Command Interface CONFIGURATION/STATUS Command—Write
PGA460-Q1 td_tc_config_stat_rd_slasec8.gifFigure 18. Time-Command Interface CONFIGURATION/STATUS Command—Read

As indicated, each CONFIGURATION/STATUS command frame consists of three data segments: subcommand field, data field, and frame checksum. The subcommands are defined and ordered by a 4-bit index field, where each subcommand can have a different data length in the data segment of the frame. Table 2 lists all PGA460-Q1 subcommands ordered according to their respective index.

Table 2. Time-Command Interface Subcommand Description(4)

INDEX DESCRIPTION DATA LENGTH (BITS) ACCESS EE
0 Temperature value 8 R N
1 Transducer frequency diagnostic value 8 24 R N
Decay period time diagnostic value 8
Noise level diagnostic value 8
2 Driver frequency (FREQ) 8 R/W Y
3 Number of burst pulses for Preset1 (P1_PULSE) 5 18 R/W Y
Number of burst pulses for Preset2 (P2_PULSE) 5
Threshold comparator Deglitch (THR_CMP_DEG) 4
Burst pulses dead-time (PULSE_DT) 4
4 Record time length for Preset1 (P1_REC) 4 8 R/W Y
Record time length for Preset2 (P2_REC) 4
5 Threshold assignment for Preset1 (P1_THR_0 to P1_THR_15)(1) 124 R/W N
6 Threshold assignment for Preset2 (P2_THR_0 to P2_THR_15)(1) 124 R/W N
7 Band-pass filter bandwidth (BPF_BW) 2 42 R/W Y
Initial AFE gain (GAIN_INIT) 6
Low-pass filter cutoff frequency (LPF_CO) 2
Noninear scaling noise level (NOISE_LVL) 5
Nonlinear scaling exponent (SCALE_K) 1
Nonlinear scaling time offset (SCALE_N) 2
Temperature-scale gain (TEMP_GAIN) 4
Temperature-scale offset (TEMP_OFF) 4
P1 digital gain start threshold (P1_DIG_GAIN_LR_ST) 2
P1 digital long-range gain (P1_DIG_GAIN_LR) 3
P1 digital short-range gain (P1_DIG_GAIN_SR) 3
P2 digital gain start threshold (P2_DIG_GAIN_LR_ST) 2
P2 digital long-range gain (P2_DIG_GAIN_LR) 3
P2 digital short-range gain (P2_DIG_GAIN_SR) 3
8 Time-varying gain Assignment (TV_GAIN0 to TV_GAIN6) 56 R/W Y
9 User-data memory (USER_1 to USER_20) 160 R/W Y
10 Frequency diagnostic window length (FDIAG_LEN) 4 46 R/W Y
Frequency diagnostic start time (FDIAG_START) 4
Frequency diagnostic error time threshold (FDIAG_ERR_TH) 3
Saturation diagnostic level (SAT_TH) 4
P1 nonlinear scaling (P1_NLS_EN) 1
P2 nonlinear scaling (P2_NLS_EN) 1
Supply overvoltage shutdown threshold (VPWR_OV_TH) 2
Sleep mode timer (LPM_TMR) 2
Voltage diagnostic threshold (FVOLT_ERR_TH) 3
AFE gain range (AFE_GAIN_RNG) 2
Low-power mode enable (LPM_EN) 1
Decouple time and temperature select (DECPL_TEMP_SEL) 1
Decouple time and temperature value (DECPL_T) 4
Disable current limit (DIS_CL) 1
Reserved 1
Driver current limit for Preset1 (CURR_LIM1) 6
Driver current limit for Preset2 (CURR_LIM2) 6
11 Echo data-dump enable (DATADUMP_EN) 1 8 R/W N
EEPROM programming password (0xD) 4
EEPROM programming successful (EE_PRGM_OK) 1
Reload EEPROM (EE_RLOAD) 1
Program EEPROM (EE_PRGM) 1
12 Echo data-dump values(2) 1024 R N
13 EEPROM user-bulk command (0x00 to 0x2B)(3) 352 R/W Y
14 Reserved
15 EEPROM CRC value (EE_CRC)
THR_CRC value (THR_CC)
16 R Y
Including the threshold level offset parameter (TH_Px_OFF).
Echo dump memory is an array of 128 samples, 8 bits/sample.
For index 13, byte 0x2B is read-only, when an index-13 write command is sent, the byte-2B data field will have no effect on the EE_CRC value.
The acronyms used in this table (for example, CURR_LIM1) are the same as those used in the Register Maps section.

The frame checksum value is generated by both the master and slave devices, and is added after the data field, while calculated as the inverted eight bit sum with carry-over on all bits in the frame. The checksum calculation occurs byte-wise starting from the most-significant bit (MSB) which is the read-write (R/W) bit in the PGA460-Q1 write operation while for PGA460-Q1 read operation, this is the MSB of the data field. In cases where the number of bits on which the checksum field is calculated is not a multiple of eight, then the checksum operation pads trailing zeros until the closest multiple eight is achieved. Zero padding is only required for the checksum calculation. The zero-padded bits should not actually be transmitted over the IO-TCI interface.

The following example, is one example of a frame checksum calculation showing the PGA460-Q1 write operation of for subcommand Index 7 (42 data bits):

  • Total number of bits for checksum generation: 1 R/W bit, 4 bits index value, 42 bits data values. The total number of bits is 47.
  • Because the checksum is calculated byte-wise, 1 trailing zero is added to achieve 6 full bytes.
  • Figure 19 shows additional checksum calculation.

The following example, is a second example of a frame checksum calculation showing the PGA460-Q1 read operation of for subcommand index 8:

  • Total number of bits for checksum generation by the PGA460-Q1 device: 56 bits data values + 8 command bits. The total number of bits is 64.
  • The 8 command bits are equal to 4-zero bits + Index[3:0] = 8 command bits which is the first byte used in the checksum calculation.
  • No trailing zeros added because the number of bits is already 56 or 7 bytes.
  • Figure 19 shows additional checksum calculation.

PGA460-Q1 checksum_calc_slasec8.gifFigure 19. Checksum Calculation

In addition, when a PGA460-Q1 write operation is issued, the PGA460-Q1 device implements an acknowledgment bit response to signify a correct data transfer occurred. In this case, if the CONFIGURATION/STATUS command time period is not detected properly, the PGA460-Q1 device does issue an acknowledgment bit. If the CONFIGURATION/STATUS command-time period is detected properly but the checksum of the transferred frame is not correct, then the PGA460-Q1 device transmits a logical 0 acknowledgment. If the CONFIGURATION/STATUS command-time period is detected properly and the checksum value matches the correct checksum, then the PGA460-Q1 device transmits a logical 1 acknowledgment.

In the case of a bit-like communication (PGA460-Q1 actively serving CONFIGURATION/STATUS command) when the bit stream is interrupted with another time command (either RUN or CONFIGURATION), the PGA460-Q1 device decodes this event as a bit-timed event in which case the execution of the initial CONFIGURATION/STATUS command continues until either a time-out error event is reached or, in the case of a continuous data transfer, the PGA460-Q1 frame checksum invalidates the incorrectly transferred frame. In the case where the bit-stream is valid but is longer than expected, the PGA460-Q1 executes on the correctly transferred frame but ignores the rest of the bit-stream.

If, during PGA460-Q1 IDLE state, the time-command interface receives a time command with pulse duration outside the limits of any of the commands, this condition is ignored and the PGA460-Q1 device remains in the IDLE state until a valid time command is received. In this case, the PGA460-Q1 does not respond with a negative acknowledgment.