SLASEC8B February 2017 – January 2019 PGA460-Q1
The PGA460-Q1 device also offers Internal diagnostics against overvoltage (OV), undervoltage (UV), overcurrent (OC), and thermal shutdown.
The OV, UV, and thermal shutdown conditions are reported through the status bits in the DEV_STAT1 register. The OC protection is implemented on the device integrated regulators; however, the effect of this protection is not reported. For proper operation and to avoid false triggering, all electrical diagnostics are passed through a 25-µs deglitch while the thermal shutdown diagnostic is passed through a 50-µs deglitch before being reported.
The OV and UV protection thresholds for the internal regulators are listed in the Specifications section. When a fault is detected, the corresponding status bit is set and it is cleared upon interface read (clear-on-read type).The input device supply on the VPWR pin defines a fixed UV-threshold level and adjustable OV-threshold level (VPWR_OV_TH) that keeps the device active while disabling the output driver. This feature allows control of power dissipation at high voltage inputs without damaging the driver. When a VPWR_UV flag is detected, any presently running TCI command finish and no new TCI commands are executed until the undervoltage condition is removed. This feature is not applicable to USART communication irrespective of the pins (RXD, TXD, or IO)
The thermal shutdown protection diagnostic monitors the temperature of the FETs of the low-side driver. In case of a thermal shutdown event, the PGA460-Q1 device disables the output drivers and re-enables them when the thermal shutdown condition is removed. After thermal shutdown recovery, the thermal shutdown status bit is set to notify the user of the action taken.
If the voltage on the VPWR pin is less than 5 V, the performance of the device is not ensured as the digital core might reset. Any settings stored in the volatile memory section of the register map will be cleared.