SLASEC8B February 2017 – January 2019 PGA460-Q1
The PGA460-Q1 device is factory programmed with the time-command interface enabled on the IO-pin. In a system where the end user uses the IO-pin in a one-wire UART mode, two possible options of enabling the one-wire UART interface on the IO-pin are available as follows:
As show in Figure 34, the data format is selected in a specific way so that a time-command interface and a UART interface can easily reproduce the pattern. The following two scenarios are possible:
In this case the master device does not generate a sync field.
As soon as the data is received by the PGA460-Q1 device, the interface on the IO-pin is toggled. The pattern in Figure 34 toggles the value of the IO_IF_SEL bit in the EEPROM memory; however, it does not program the EEPROM. Therefore, as soon as the PGA460-Q1 Interface is set to the target interface, the master controller must issue a command to program the EEPROM with the desired configuration.
In case of toggling the selection pattern for the IO interface option, a STAT2 bit is triggered to 1. Upon reading, the STAT2 bit is cleared.