SLASEC8B February 2017 – January 2019 PGA460-Q1
The PGA460-Q1 device is equipped with two communication interfaces, each with a designated pin. The time-command interface is connected to the IO pin which is an open-drain output structure with an internal 10-kΩ pullup resistor capable of communicating at battery level voltage. The asynchronous UART interface can communicate on the IO pin and is also connected to the RXD and TXD pins. A third Interface option is to use the synchronous USART interface which is available only at the RXD and TXD pins. This communication uses SCLK pin for a serial clock input and is the fastest data-rate mode. USART communication on RXD and TXD pins is available at a 3.3-V or 5-V CMOS level depending on the configured IOREG voltage as described in the TEST Pin Functionality section.
Because the system is unlikely to simultaneously use both the time-command interface and the UART interface, the PGA460-Q1 device can disable the IO pin transceiver to preserve power. To do so, the IO_IF_SEL bit must be 0, and the IO_DIS bit must be 1 which immediately disables the IO pin transceiver upon which communication is only possible through the RXD and TXD pins. Setting the IO_DIS bit back to 0 does not re-enable the IO interface. If the IO_DIS bit was set unintentionally, the device can recover the IO interface (reset the IO_DIS bit to 0) upon power-cycle; however, when the value of this bit is programmed in the EEPROM, the PGA460-Q1 device always follows the EEPROM-programmed value on power up.