SLASEC8B February 2017 – January 2019 PGA460-Q1
The PGA460-Q1 implements a cyclic redundancy check (CRC) that is a self-contained algorithm to verify the integrity of the EEPROM stored data and threshold settings. When an EEPROM program or EEPROM-reload operation is executed, or when a threshold register is written, the CRC controller calculates the correct CRC value and writes it to the corresponding registers: For EEPROM memory, this value is written to the EE_CRC register. For threshold settings, this value is written to the THR_CRC register.
A CRC is performed at power-up when an EEPROM reload command is issued. The CRC algorithm for all memory blocks is the same and is shown in Equation 6 with an initial seed value of 0xFF and uses MSB ordering. This calculation is performed byte wise starting from the MSB to the LSB. The data is concatenated as follows:
The results of the CRC check are stored in the DEV_STAT0 register and can be directly read through the UART interface, while the time-command interface reports these in Status Bit3 and Status Bit1. For more information on the time-command interface status bits, see the Time-Command Interface section. For the default values, see the Register Maps section.