SLASEC8B February 2017 – January 2019 PGA460-Q1
The PGA460-Q1 device implements an option to connect the UART interface on the IO pin. In this case, the UART interface becomes a battery-voltage one-wire interface (OWI) because the IO pin is an open-drain type and implements a 10-kΩ pullup to the VPWR pin. This feature is possible because the communication on the UART interface is unidirectional at all times.
To enable the one-wire UART interface the IO_IF_SEL bit must be set to 1, in which case the internal communication multiplexers connect the digital logic of the UART interface to the IO-pin transceiver. The RXD and TXD pins are not changed and their operation is preserved.
Although UART communication through the IO pin, RXD pin, and TXD pin is allowed simultaneously, a possibility can occur for data collision in the case when the master controller is communicating to the IO pin while another master-controlled is trying to communicate through the UART transceiver on the RXD and TXD pins. Therefore, in an application where the IO pin is used, the RXD pin must be connected to the Hi-Z state which would cause the UART transceiver to disable when the PGA460-Q1 device has been enabled. For a detailed explanation, see the Interface Description section.
When UART sync mode is selected while the IO_IF_SEL bit is set to 1 (IO pin to UART interface) the IO transceiver is disabled.